Back to results
US 8,298,876 B2Granted
Methods for normalizing strain in semiconductor devices and strain normalized semiconductor devices
AssigneeInternational Business Machines Corporation
InventorsBruce Balch, Kerry Bernstein, John Joseph Ellis-Monaghan, Nazmul Habib
Life of this patent
Estimating the term…
Abstract
A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.
Claims21
A method, comprising:
- forming first and second field effect transistors of an integrated circuit;
- forming a stress layer over said first and second field effect transistors, said stress layer having a first thickness, said stress layer inducing strain in channel regions of said first and second field effect transistors;
- and
- selectively thinning said stress layer over at least a portion of said second field effect transistor to a second thickness, a region of said stress layer having said first thickness remaining over at least a portion of said first transistor wherein before said selectively thinning said stress layer, a first difference between amounts of strain in channel regions of said first and second field effect transistors is greater than a second difference between amounts of strain in said channel regions of said first and second field effect transistors after said selectively thinning said stress layer.
1 more element
A method, comprising:
- determining spatial relationships between design shapes of selected levels of a design of field effect transistors of an integrated circuit;
- generating an estimate of strains that would be induced in channel regions of said field effect transistors as a function of the thickness of a stress layer formed over said field effect transistors based on said spatial relationships;
- generating a stress layer photomask based on said design shapes of said selected design levels and said estimate of strains;
- forming said stress layer over said first and second field effect transistors, said stress layer having a first thickness, said stress layer inducing strain in channel regions of said first and second field effect transistors;
- and
- using said stress layer photomask, selectively thinning said stress layer from a first thickness to a second thickness over at least portions of field effect transistors of a first set of said field effect transistors, a region of said stress layer having said first thickness remaining over at least portions of field effect transistors of a second set of said field effect transistors wherein said design shapes consist of dielectric isolation shapes of a first design level of said selected design levels and gate electrode shapes of a second design level of said selected design levels, said gate electrode shapes defining gate electrodes of said field effect transistors and in combination with said dielectric isolation shapes defining source/drains and channel regions of said field effect transistors.
3 more elements
Dependencies are inferred from the claim text.