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US 8,298,875 B1Granted
Method for fabrication of a semiconductor device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Paul Lim
Life of this patent
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Abstract
A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.
Claims19
A method to fabricate a junction-less transistor comprising:
- forming a transistor body with variable doping, said body comprising a first portion of high dopant concentration and a second portion of at least 1/10 less dopant concentration, and then a transistor channel length is defined by an etch step,
- wherein said etch step removes regions of at least one of said portions, and
- said first portion and said second portion are of the same dopant type, and
- said transistor body comprises source, drain, and channel of said junction-less transistor.
1 more element
A method to fabricate a junction-less transistor comprising:
- forming a transistor body with variable doping, said body comprising a first portion of high dopant concentration and a second portion of at least 1/10 less dopant concentration,
- wherein said first portion overlays said second portion, and
- a transistor channel length is defined by an etch step, and
- said first portion and said second portion are of the same dopant type, and
- said transistor body comprises source, drain, and channel of said junction-less transistor.
2 more elements
Dependencies are inferred from the claim text.