Single-chip flash device with boot code transfer capability

A single-chip flash device comprising:

• a clocked-data interface to a host bus that connects to a host;
• a bus transceiver for detecting and processing commands sent over the host bus;
• a buffer for storing data sent over the host bus;
• an internal bus coupled to the buffer;
• a random-access memory (RAM) for storing instructions for execution, the RAM on the internal bus;
• a central processing unit, on the internal bus, the CPU accessing and executing instructions in the RAM;
• a flash-memory controller, on the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to a flash bus;
• flash mass storage blocks coupled to the flash-memory controller by the flash bus, and controlled by the flash-control signals;
• a direct-memory access (DMA) engine, on the internal bus, for transferring data over the internal bus;
• and a flash programming engine, activated by a reset, for initially programming the DMA engine to transfer an initial program of instructions from the flash mass storage blocks to the RAM before the CPU begins execution of instructions after the reset;
• whereby the initial program of instructions is transferred from the flash mass storage blocks to the RAM before execution by the CPU begins;
• wherein the transfer means further comprises:
• control register means for indicating a first mode and a second mode;
• wherein the CPU fetches instructions from the RAM during the first mode;
• wherein the CPU fetches instructions from the second RAM during the second mode;
• and toggle means, activated by execution of an initial boot loader, for changing the control register means from the first mode to the second mode before the initial program of instructions is executed by the CPU;
• and wherein the flash mass storage blocks are initially readable after a reset before receiving a command and a physical address over the flash bus;
• wherein the flash mass storage blocks send data in a first page over the flash bus after the reset and before receiving a command and a physical address over the flash bus.

A multi-interface microcontroller comprising:

• input/output interface circuit means for establishing communication with a host computer, wherein the input/output interface circuit means includes a Multimedia Card (MMC) interface circuit or wherein the input/output interface includes a eMMC bus, a Universal Flash Storage (UFS) bus, a Memory-Stick bus, a PCI Express bus, an IDE bus, or a Serial ATA (SATA) bus;
• flash bus means for connecting to a flash memory, the flash bus means carrying address, data, and commands to the flash memory;
• wherein the flash memory stores an initial boot loader, an extended boot sequence, and a complete boot sequence in a non-volatile memory;
• first volatile memory means for storing first instructions for execution;
• second memory interface means for interfacing to a second volatile memory means for storing second instructions for execution;
• processor means, coupled to the input/output interface circuit means, for fetching and executing the first instructions in the first volatile memory means during a first mode and fetching and executing the second instructions from the second volatile memory means during a second mode;
• flash-memory controller means for generating flash-control signals and for buffering commands, addresses, and data to the flash bus means;
• hardwired initializer means, activated by a reset signal, for activating the flash-memory controller means to read the initial boot loader from the flash memory, and for writing the initial boot loader as the first instructions to the first volatile memory means;
• initial boot loader execution means for activating the processor means to fetch and execute the first instructions from the first volatile memory means, the initial boot loader execution means for activating the flash-memory controller means to read the extended boot sequence from the flash memory, for writing the extended boot sequence as the second instructions to the second volatile memory means;
• and extended boot sequence execution means for activating the processor means to fetch and execute the second instructions from the second volatile memory means, the extended boot sequence execution means for activating the flash-memory controller means to read the complete boot sequence from the flash memory, and for writing the complete boot sequence as additional second instructions to the second volatile memory means;
• wherein the transfer means further comprises:
• control register means for indicating a first mode and a second mode;
• wherein the processor means fetches instructions from the first volatile memory means during the first mode;
• wherein the processor means fetches instructions from the second volatile memory means during the second mode;
• and toggle means, activated by the initial boot loader execution means, for changing the control register means from the first mode to the second mode before the extended boot sequence execution means is activated.