Multiplexed latching valves for microfluidic devices and processors

A microfluidic logic circuit comprising:

• an array of membrane valves, the array comprising a latching valve and a plurality of logic valves, wherein the logic valves are part of a single monolithic structure and wherein the latching valve and the logic valves are in fluid communication with each other to form a logic gate structure, and wherein the latching valve comprises:
• a valve input configured to receive application of a pressure or a vacuum;
• a valve control configured to receive application of a pressure, vacuum, or neither;
• a valve output;
• and a first normally-closed elastomer membrane configured such that the application of a pressure or a vacuum to the valve input and application of a pressure, a vacuum or neither to the valve control causes the membrane to deflect according to the following pneumatic logic:
• Valve Input
• Valve Control
• Valve Output
• Pressure
• Pressure
• Closed
• Pressure
• Vacuum
• Open
• Pressure
• Neither
• Open if input pressure large
• enough to force valve open
• Vacuum
• Pressure
• Closed
• Vacuum
• Vacuum
• Open
• Vacuum
• Neither
• Closed;
• and further wherein each of the logic valves comprises a valve input configured to receive application of a pressure or a vacuum;
• a valve control configured to receive application of a pressure, vacuum, or neither;
• a valve output;
• and a normally-closed elastomer membrane configured such that the application of a pressure or a vacuum to the valve input and application of a pressure, a vacuum or neither to the valve control causes the membrane to deflect according to said pneumatic logic.