Overlay instruction accessing unit and overlay instruction accessing method

#The present invention relates to an overlay instruction accessing unit and overlay instruction accessing method, as well as an apparatus and method for compressing and storing a program.

#With the increase of the scale of a System on Chip (SOC) and the development of application programs for the SOC, there is a need to integrate an embedded processor into the whole system in order to provide a high performance based on optimized instructions and structures. One of these generic architectures is to integrate digital signal processors (DSPs) into the system. Application programs built on this kind of platform can take advantage of the high performance provided by the DSPs to process digital media.

#Integrating the processing units into the system improves the programmability of the SOC. However, the need for memories for storing instructions executed by these processing units increases correspondingly, because each of the processing units requires an individual instruction memory to store instructions to be executed. The problem is worse for a Single Program Multiple Data (SPMD) application in a multi-core architecture. In this case, since each processing unit of the multi-core processor needs to read and execute a same program, it is required to duplicate the program into an instruction memory for each processing unit so as to be executed by it, which increases the need for the instruction memories. Since the instruction memories are major sources of the cost of the system (especially for the SPMD model), integrating the processing units into the system correspondingly increases the cost of the system.

#The above and other objects, features, and advantages of the present invention will become more apparent from the detailed description of embodiments of the present invention in conjunction with the attached drawings in which

#FIG. 1 is a block diagram of an apparatus for compressing and storing a program according to the present invention.

#FIG. 2 is a flow diagram of a method for compressing and storing a program performed by the apparatus shown in FIG. 1 according to present invention.

#Hereinafter, embodiments of the present invention are described with respect to the figures. It is to be understood that the embodiments described herein are only illustrative, but not to limit the scope of the present invention. It will be appreciated by those skilled in the art that various modifications and combinations can be made to the embodiments without departing from the scope of the present invention.

#In general, a program is consisted of several instruction segments, and the instruction segments are linked to each other by jump instructions. When a processing unit executes the program, the processing unit executes these instruction segments sequentially and independently due to the data independence among the respective instruction segments, and jumps to a next instruction segment according to an encountered jump instruction after executing an instruction segment. The jump instructions comprise jump, call, and so on which indicate invoking relationships among the respective instruction segments in the program.

#Based on this characteristic, if viewed from a sequence diagram, the invoking relationships among the respective instruction segments can be regarded as a list. For an H.264 decoder, for example, its sequence diagram is consisted of the steps of parsing, idct, intra/inter prediction, reconstruction, in-loop filtering, and so on. When processing a data stream, the H.264 decoder performs these steps sequentially on the data stream, and each of the steps is independent from the other steps when executed.