Systematic method for variable layout shrink
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu-Chieh Hsu, Louis Chao-Chiuan Liu, Lee-Chung Lu, Yi-Kan Cheng
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu-Chieh Hsu, Louis Chao-Chiuan Liu, Lee-Chung Lu, Yi-Kan Cheng
Estimating the term…
A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.
A method for integrated circuit design, the method comprising:
A method for integrated circuit design, the method comprising:
A method for integrated circuit design, the method comprising:
Dependencies are inferred from the claim text.