Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout
AssigneeFujitsu Limited
InventorsMasashi Arayama, Sumiko Makino
Life of this patent
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Abstract
A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
Claims1
A macro layout verification apparatus comprising:
- a unit configured to assume as a virtual wiring line a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line, the unused intra-macro channel capable of being used for wiring a wiring line of a chip-level layout of a semiconductor device;
- a unit configured to calculate a parallel wiring length along which said virtual wiring line and said intra-macro wiring line run;
- a unit configured to compare said parallel wiring length with a reference value defined as a design rule to verify a layout of a macro to be placed as a functional block on the chip-level layout;
- and
- a unit configured to output information concerning said virtual wiring line when said parallel wiring length exceeds the reference value defined as a design rule.
Dependencies are inferred from the claim text.