Fast routing of custom macros

#The present invention relates to integrated circuits, and more specifically, to routing the connections between components of an integrated circuit (IC).

#Integrated circuit layout, also known as IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. When using a standard process—where the interaction of the many chemical, thermal, and photographic variables are known and carefully controlled—the behavior of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. A layout engineer's job is to place and connect all the components that make up a chip so that they meet all criteria. Typical goals are performance, size, and manufacturability.

#Initially, IC design layout was done by hand using opaque tapes and films, much like the early days of PCB design. Modern IC layout is done with the aid of IC layout editor software, or even using EDA (Electronic Design Automation) tools, including place and route tools or schematic driven layout tools. The manual operation of choosing and positioning the geometric shapes is informally known as “polygon pushing”.

#The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIG. 1 shows a data flow diagram according to one embodiment of the present invention;

#FIGS. 2a and 2b show an example of a hierarchical schematic diagram (FIG. 2a) and a flat, unplaced layout (FIG. 2b) created there from;

#With reference now to FIG. 1, a data flow diagram for a system 100 for fast routing of custom macros according to one embodiment of the present invention is shown. The system may be implemented, for example, on a computing system as shown in FIG. 5. Of course, the system could be formed independently of any other computing system if needed.

#The system 100 includes placement engine 102, a flat layout engine 104 and a back annotation engine 106. The placement engine 102 receives an electronic representation of a hierarchical structure 108. The hierarchical structure 108 may be any representation of a circuit diagram that includes multiple building blocks. Examples of the building blocks could include NAND gates and the next higher level could be, for example, a J-K flip-flop.

#From the hierarchical structure 108 the placement engine may create a hierarchical, placed layout 110. The placed layout contains the schematic as it may be laid out in a silicon chip and represents the circuit as having hierarchical structure.