US 8,286,113 B1 · Verification of logic core implementation

Abstract

A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.

Claims20

Dependent claims

A method for verifying implementation of a logic core in a complete bitstream, the method comprising:

using at least one processor programmed to perform operations including:
extracting a logic core bitstream from the complete bitstream;
comparing the logic core bitstream to a reference bitstream of the logic core for a target device;
in response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, storing a data value indicating that the logic core implementation contained in the complete bitstream is verified;
and
in response to a discrepancy in the comparison of the logic core bitstream and the reference bitstream, storing a data value indicating that the logic core implementation contained in the complete bitstream is not verified.

3 more elements

A system for verifying implementation of a logic core in a complete bitstream, the system comprising:

one or more processors;
and
a memory arrangement coupled to the one or more processors, wherein the memory arrangement is configured with instructions that when executed by the one or more processors cause the one or more processors to perform operations including:
extracting a logic core bitstream of the logic core from the complete bitstream;
comparing the logic core bitstream to a reference bitstream of a verified logic core implementation for a target device;
in response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, storing a data value indicating that the logic core implementation extracted from the complete bitstream is verified;
and
in response to a discrepancy in the comparison of the logic core bitstream and the reference bitstream, storing a data value indicating that the logic core implementation extracted from the complete bitstream could not be verified.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/004,183Filed 11 Jan 2011

Granted

9 Oct 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 2115/08
Details relating to the type of the circuit: intellectual property [IP] blocks or IP cores

Abstract

Facts

Application

13/004,183Filed 11 Jan 2011

Granted

9 Oct 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 2115/08
Details relating to the type of the circuit: intellectual property [IP] blocks or IP cores

Verification of logic core implementation

Life of this patent

Abstract

Claims20

Verification of logic core implementation

Life of this patent

Abstract

Claims20