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US 8,286,108 B2Granted
System and method for synthesis reuse
AssigneeCadence Design Systems, Inc.
InventorsLuciano Lavagno, Alex Kondratyev, Yoshinori Watanabe
Life of this patent
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Abstract
A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.
Claims24
A method of synthesis of multiple implementations of an integrated circuit design, comprising:
- providing a model of the design comprising an algorithm implemented by the design;
- using a computer system to perform steps of:
- providing a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- providing a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the first constraint file to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.
9 more elements
A method of synthesis of multiple implications of an integrated circuit design, comprising:
- providing a model of the design comprising an algorithm implemented by the design;
- using a computer system to perform steps of:
- providing a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- providing a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the constraint files to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.
9 more elements
A computer system, comprising:
- a CPU;
- a storage;
- and a bus coupling the CPU to the storage;
- wherein the storage stores a code for execution by the CPU, the code performing a method of synthesis of multiple implementations of an integrated circuit design comprising:
- receiving a model of the design comprising an algorithm implemented by the design;
- receiving a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- receiving a second constraint file including at least one second constraint upon. implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the first constraint file to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.
12 more elements
A computer system, comprising:
- a CPU;
- a storage;
- and a bus coupling the CPU to the storage;
- wherein the storage stores a code for execution by the CPU, the code performing a method of synthesis of multiple implementations of an integrated circuit design comprising:
- receiving a model of the design comprising an algorithm implemented by the design;
- receiving a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- receiving a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the constraint files to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.
12 more elements
A computer readable storage device storing code for performing a method of synthesis of multiple implementations of an integrated circuit design, wherein the method comprises:
- receiving a model of the design comprising an algorithm implemented by the design;
- receiving a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- receiving a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the first constraint to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.
8 more elements
A computer readable storage device storing code for performing a method of synthesis of multiple implementations of an integrated circuit design, wherein the method comprises:
- receiving a model of the design comprising an algorithm implemented by the design;
- receiving a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- receiving a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the constraint files to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.
8 more elements
Dependencies are inferred from the claim text.