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US 8,286,066 B2Granted
Non-volatile memory with bi-directional error correction protection
AssigneeMicron Technology, Inc.
InventorsChristopher Bueb, Shaul Halabi
Life of this patent
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Abstract
Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with bi-directional error correction protection. In some embodiments, multiple multi-level parity cells are used to represent parity values stored in codewords of an NVM device. Other embodiments may be described and claimed.
Claims18
A method, comprising:
- writing, in a first programming iteration, a first parity value of a plurality of parity values to a plurality of multilevel parity cells device by level shifting at least one of the plurality of multilevel parity cells in a first direction, the plurality of parity values having an ascending sequence order;
- and writing in a second programming iteration, a second parity value of the plurality of parity values to the plurality of multilevel parity cells by level shifting at least one of the plurality of multilevel parity cells in the first direction, the second parity value occurring earlier in the ascending sequence order than the first parity value and the second programming iteration occurs after the first programming iteration without an intervening erase operation.
An apparatus comprising memory having instructions that, when executed, cause the apparatus to:
- write, in a first programming iteration, a first parity value of a plurality of parity values to a plurality of multilevel parity cells of a non-volatile memory (NVM) device by level shifting at least one of the plurality of multilevel parity cells in a first direction, the plurality of parity values having an ascending sequence order;
- and write, in a second programming iteration, a second parity value of the plurality of parity values to the plurality of multilevel parity cells by level shifting at least one of the plurality of multilevel parity cells in the first direction, the second parity value occurring earlier in the ascending sequence order than the first parity value and the second programming iteration occurs after the first programming iteration without an intervening erase operation.
A non-volatile memory (NVM) device, comprising:
- a plurality of codewords, each of the plurality of codewords including:
- a plurality of data cells configured to store a data value in the codeword;
- and a plurality of parity cells configured to be programmed to write in a first and a second parity value from a plurality of parity values in a first and a second programming iteration respectively by level shifting at least one of the plurality of parity cells in a first direction;
- wherein the second programming iteration occurs after the first programming iteration without any intervening erase operation, and the second parity value occurring earlier than the first parity value in an ascending sequence order formed by the plurality of parity values.
1 more element
Dependencies are inferred from the claim text.