Scheme for erasure locator polynomial calculation in error-and-erasure decoder

A circuit comprising:

• a plurality of registers (i) storing a plurality of current values and (ii) generating an output signal carrying said current values such that said current values form a plurality of coefficients of an erasure locator polynomial in an error-and-erasure decoder;
• a plurality of multiplier modules generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants;
• a plurality of first modules generating a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure elements of an erasure location vector;
• and
• a plurality of summing modules (i) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values and (ii) loading said next values into said registers in place of said current values.

A system comprising:

• a first circuit configured to generate an erasure locator polynomial in response to all of (a) an erasure location vector and (b) a plurality of constants, wherein each of said constants is a multiplication factor in a respective one of a plurality of multiplier modules;
• a second circuit configured to generate a plurality of syndromes in response to an input codeword;
• and
• a third circuit configured to generate an output signal carrying a reconstructed codeword in response to all of (i) said erasure locator polynomial, (ii) said syndromes and (iii) said input codeword, wherein (a) said first circuit comprises a plurality of registers configured to (i) store a plurality of current values and (ii) generate an intermediate signal carrying said current values such that said current values form a plurality of coefficients of said erasure locator polynomial, (b) said multiplier modules are configured to generate a plurality of first values by multiplying said current values by said respective constants and (c) said first circuit further comprises a plurality of first modules configured to generate a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure values of said erasure location vector.