Word-serial cyclic code encoder
AssigneeMarvell International Ltd.
InventorChengKuo Huang
Life of this patent
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Abstract
A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words, respectively.
Claims17
An encoder configured to encode cyclic codes, the encoder comprising:
- a first word register and a second word register each having an input and an output;
- an input adder that is coupled to the output of the first word register, the input adder being configured to receive input words and to output corresponding feedback words;
- a first adder array that is coupled between the input of the first word register and the output of the second word register;
- a feedback loop that is configured to selectively transmit feedback words to the input of the second word register and an input of the first adder array;
- a controller that is configured to cause the encoder to operate in an input mode and an output mode, during the input mode, feedback words are sequentially transmitted on the feedback loop, a number of bits per a feedback word being different from a word width of at least one of the first and second registers, and states of the first word register and the second word register are updated, while during the output mode, states of the first word register and the second word register are sequentially shifted out of the first word register as parity words;
- and
- a multiplexer to output the input words and parity words from the encoder such that each parity word is appended to a corresponding input word.
A method for encoding cyclic codes, the method comprising:
- during an input mode:
- adding a state of a first word register with an input word to generate a corresponding feedback word,
- transmitting the feedback word to the first word register and a second word register, a number of bits per a feedback word being different from a word width of at least one of the first and second registers,
- weighting the feedback word by a first weight array prior to the feedback word being received by the first word register,
- weighting the feedback word by a second weight array prior to the feedback word being received by the second word register,
- updating a state of the second word register based on the weighted second feedback word, and
- updating a state of the first word register based on the weighted first feedback word and the state of the second word register;
- during an output mode:
- sequentially shifting states of the first and second word registers out of the first word register as parity words, and
- appending the parity words to an input word.
A storage device, comprising:
- a memory medium;
- an interface coupled to the memory medium that includes:
- a first word register and a second word register each having an input and an output,
- an input adder that is coupled to the output of the first word register and configured to receive input words and to output a corresponding feedback word,
- a first adder array that is coupled between the input of the first word register and the output of the second word register,
- a feedback loop that is configured to selectively transmit weighted feedback words to the input of the second word register and an input of the first adder array;
- a controller that is configured to cause the storage device to operate in an input mode and an output mode, during the input mode, feedback words are sequentially transmitted on the feedback loop, a number of bits per a feedback word being different from a word width of at least one of the first and second registers, and states of the first word register and the second word register are updated, while during the output mode, states of the first word register and the second word register are shifted out of the first word register as parity words;
- and
- a writing device that is configured to write a codevector to the memory medium, the codevector including the input words and the parity words.
Dependencies are inferred from the claim text.