Nonvolatile memory device and method of operating the same
AssigneeHynix Semiconductor Inc.
InventorJun Rye Rho
Life of this patent
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Abstract
A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.
Claims11
A nonvolatile memory device, comprising:
- a memory cell array configured to comprise memory cells coupled by bit lines and word lines;
- a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group;
- and
- an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.
A method of operating a nonvolatile memory device comprising a plurality of memory cells and page buffers coupled to the memory cells, the method comprising:
- performing a first read operation using a first read voltage on memory cells, selected from among the plurality of memory cells, and storing first data, read by the first read operation, in second latches of the page buffers;
- classifying the page buffers into two or more groups and determining whether erroneously read data exist in the first data stored in the second latches of each of the two or more groups;
- if the erroneously read data is determined to exist in the first data stored in the second latches of a first group of the two or more groups, performing a second read operation on the first group using a second read voltage less than the first read voltage, and storing second data, read by the second read operation, in first latches of page buffers belonging to the first group;
- storing a result of performing a logic operation on the first and second data in third latches of the page buffers belonging to the first group;
- and
- determining whether a first logic data exists in the data stored in the third latches of the page buffers belonging to the first group,
- wherein if the first logic data is determined to exist in the data stored in the third latches, counting a number of the first logic data, determining whether the number of first logic data is a number of bits or less for which error correction is possible, and
- if the number of first logic data is determined to be the number of bits or less for which error correction is possible, performing the error correction for the first group.
Dependencies are inferred from the claim text.