US 8,286,041 B2Granted

Semiconductor integrated circuit and method of saving and restoring internal state of the same

AssigneeRenesas Electronics Corporation

InventorsTatsuya Kawasaki, Tsuneki Sasaki, Shuichi Kunie

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Abstract

A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection. The semiconductor integrated circuit further includes a backup control circuit configured to control the scan chain in a saving operation in the normal mode such that the internal state data is stored in the memory circuit without passing through the second flip-flops, in the restoring operation in the normal mode such that the internal state data from the first selecting circuit is set in the first flip-flops without passing through the second flip-flops, and in the scan path test mode such that the test data is shifted in the series connection.

Claims14

Dependent claims

A semiconductor integrated circuit, comprising:

a scan chain which comprises:
first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein said first flip-flops and said second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register;
a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of said first flip-flops and read from a memory circuit in a restoring operation in a normal mode to said series connection;
and
a second selecting circuit provided between one of said second flip-flops and one of said second flip-flops subsequent to said one second flip-flop in said series connection and configured to select an output of said one second flip-flop in the scan path test mode and an output of one of said first flip-flops which is previous to said one second flip-flop or a series connection of said second flip-flops including said one second flip-flop;
and
a backup control circuit configured to control said scan chain in a saving operation in the normal mode such that the internal state data is stored in the memory circuit without passing through said second flip-flops, in the restoring operation in the normal mode such that the internal state data from said first selecting circuit is set in said first flip-flops without passing through said second flip-flops, and in the scan path test mode such that the test data is shifted in the series connection.

4 more elements

A method of saving and restoring an internal state in a semiconductor integrated circuit, comprising:

providing a scan chain which comprises:
first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein said first flip-flops and said second flip-flops are connected in a series connection to be operable as a shift register;
and
a first selecting circuit connected to a front stage of said series connection;
selecting in said first selecting circuit, a test data in the scan path test mode and internal state data indicating an internal state of said first flip-flops and outputted from a memory circuit in a restoring operation in a normal mode;
passing the test data through said scan chain in the scan path test mode;
saving the internal state data in said memory circuit without passing through said second flip-flops, in a saving operation in the normal mode;
and
restoring the internal state data in said first flip-flops without passing through said second flip-flops in the restoring operation in the normal mode,
wherein said providing further comprises providing a second selecting circuit between one of said second flip-flops and one of said first flip-flops subsequent to said one second flip-flop, and
wherein said saving comprises selecting an output of said one second flip-flop in the scan path test mode and an output of a last one of said first flip-flops which is at least previous to said one second flip-flop in the saving operation in the normal mode.

8 more elements

Dependencies are inferred from the claim text.