Highly reliable storage system and internal network thereof

A storage controller apparatus that communications with a host computer and a storage apparatus comprising:

• at least one processing unit;
• a plurality of memory units;
• a plurality of switch units;
• wherein each of the plurality of switch units are connected to said at least one processing unit and each of the plurality of memory units such that said at least one processing unit is configured to communicate with each of the plurality of memory units via each of the plurality of switch units,
• wherein said at least one processing unit sends to one of said memory units, via one of said switch units, a request packet for requesting data read or data write upon request of the host computer,
• wherein, if said one of said memory units receives the request packet via said one of said switch units, said one of said memory units out puts data or stores data in response to a request of the received request packet, and sends to said at least one processing unit, via said one of said switch units, a response packet associated with the received request packet,
• wherein said at least one processing unit determines whether the response packet associated with the request packet has been received within a first time period from the sending of the request packet,
• wherein said one of said switch units determine whether the response packet sent from said one of said memory units has passed through said one of said switch units within a second time period from a passage of the request packet associated with the response packet, the second time period is shorter than the first time period,
• wherein, if said at least one processing unit determines that the response packet associated with the request packet has not been received within the first time period since the sending of the request packet, said at least one processing unit determines that a failure occurs in said one of said plurality of said switch units, and disables said one of said plurality of said switch units,
• wherein, if said one of said switch units determines that the response packet has not passed through said one of said plurality of said switch units within the second time period since the passage of the request packet associated with the response packet, said one of said switch units determines that a failure occurs in said one of said plurality of said memory units, and disables said one of said plurality of said memory units.

A method for detecting a failure occurred in a storage controller apparatus, wherein said storage controller apparatus includes at least one processing unit, a plurality of memory units and a plurality of switch units, and communicates with a host computer and a storage apparatus, wherein each of the plurality of switch units are connected to said at least one processing unit and each of the plurality of memory units such that said at least one processing unit can communicate with each of the plurality of memory units via each switch unit, the method comprising the steps of:

• sending from said at least one processing unit to one of said plurality of said plurality of said memory units, via one of said plurality of said switch units, a request packet for requesting data read or data write upon request of the host computer;
• receiving by said one of said plurality of said plurality of said memory units the request packet via said one of said plurality of said switch units, outputting data from or storing data in said one of said plurality of said memory units in response to a request of the received request packet, and sending from said one of said plurality of said memory units to said at least one processing unit, via said one of said plurality of said switch units, a response packet associated with the received request packet;
• determining by said at least one processing unit whether or not the response packet associated with the request packet has been received within a first time period since the sending of the request packet;
• determining by said one of said plurality of said switch units whether or not the response packet sent from said one of said plurality of said memory units has passed through said one of said plurality of said switch units within a second time period since a passage of the request packet associated with the response packet, wherein the second time period is shorter than the first time period;
• determining by said at least one processing unit that a failure occurs in said one of said plurality of said switch units, and disabling said one of said plurality of said switch units, if said at least one processing unit determines that the response packet associated with the request packet has not been received within the first time period since the sending of the request packet;
• determining by said one of said plurality of said switch units that a failure occurs in said one of said plurality of said memory units, and disabling said one of said plurality of said memory units, if said one of said plurality of said switch units determines that the response packet has not passed through said one of said plurality of said switch units within the second time period since the passage of the request packet associated with the response packet.