Flash memory devices with high data transmission rates and memory systems including such flash memory devices

A memory system comprising:

• a) a NAND flash memory package that includes:
• a memory core;
• a first package terminal that is configured to receive a clock signal;
• a second package terminal that is configured to receive a read-enable signal;
• a third package terminal that is configured to receive a write-enable signal;
• fourth package terminals that are configured to receive data to be written in the memory core and an address;
• and
• a data input/output buffer electrically connected to the first and fourth package terminals;
• and
• b) a flash controller that is configured to control the NAND flash memory package,
• wherein the write-enable signal is active at a first logic state to thereby enable writing to the memory core,
• wherein throughout a period when the write-enable signal is maintained at the first logic state, the data input/output buffer circuit is configured to receive the data through the fourth package terminals in synchronization with rising and falling edges of the clock signal.

A memory system comprising:

• a) a NAND flash memory package that includes:
• a memory core;
• a first package terminal configured to receive a clock signal;
• a second package terminal configured to receive a mode selection signal indicating data output and input modes;
• third package terminals configured to receive data to be written in the memory core and an address;
• and
• a data input/output buffer electrically connected to the first and third package terminals;
• and
• b) a flash controller that is configured to control the NAND flash memory package,
• wherein throughout an activation period of the mode selection signal while the mode selection signal is maintained at a first logic level indicating the data input mode, the data input/output buffer circuit is configured to receive the data though the third package terminals in synchronization with rising and falling edges of the clock signal.

A method of operating a flash memory package that includes a memory cell array and a data input/output buffer circuit that is configured to receive a clock signal at a first input, a signal designating a data input mode at a second input, and data that is to be written to the memory cell array at a plurality of data input/output pins, the method comprising:

• receiving the signal designating the data input mode at the second input, the signal designating the data input mode being active at a first logic level;
• and
• receiving data in the data input/output buffer that is to be written to the memory cell array at the plurality of data input/output pins in synchronization with rising and falling edges of the clock signal when the signal designating the data input mode is active,
• wherein the signal designating the data input mode is received at the first logic level throughout the step of receiving data,
• wherein the flash memory package has a first row of pins on a first side edge of the package and a second row of pins on a second side edge of the package that is opposite the first side edge of the package, wherein the first input and the plurality of data input/output pins comprise respective ones of the first row of pins, and wherein none of the plurality of data input/output pins comprise any of the second row of pins.