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US 8,286,012 B2Granted
Architecture incorporating configurable controller for reducing on chip power leakage
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsSatinder Singh Malhi, Arant Agrawal
Life of this patent
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Abstract
The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
Claims19
A power control module comprising:
- a read only memory (ROM) module;
- a main control unit operatively coupled to the ROM module;
- a programmable control register bank operatively coupled to the main control unit;
- a minimum leakage vector (MLV) chain shift unit operatively coupled to the programmable control register bank;
- and
- a peripheral gating and reset signal generation unit operatively coupled to a device peripheral.
3 more elements
A system comprising:
- a minimum leakage vector power control module;
- and
- a device peripheral coupled to the minimum leakage vector power control module,
- wherein the minimum leakage vector power control module comprises:
- a read only memory (ROM) module;
- a main control unit operatively coupled to the ROM module;
- a programmable control register bank operatively coupled to the main control unit;
- a minimum leakage vector (MLV) chain shift unit operatively coupled to the programmable control register bank;
- and
- a peripheral gating and reset signal generation unit operatively coupled to the device peripheral, and
- wherein the MLV chain shift unit is used to shift an MLV into a corresponding peripheral using an existing scan chain circuitry of the peripheral.
8 more elements
Dependencies are inferred from the claim text.