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US 8,285,971 B2Granted
Block driven computation with an address generation accelerator
AssigneeInternational Business Machines Corporation
InventorsRavi K. Arimilli, Balaram Sinharoy
Life of this patent
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Abstract
A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.
Claims19
A processor, comprising:
- an instruction sequencing unit that sequences processing of compiled program code by the processor, wherein the compiled program code includes executable instructions, an operand data structure describing a plurality of sequentially processed computation blocks, and block computation commands invoking processing of the computation blocks, wherein the instruction sequencing unit asserts an initiation signal in response to detecting a block computation command in the compiled program code;
- at least one execution unit that, responsive to receipt of executable instructions of the complied program code from the instruction sequencing unit, executes the executable instructions;
- at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit;
- data storage that buffers the operand data structure of the compiled program code, wherein the operand data structure describes the plurality of sequentially processed computation blocks of the compiled program code not executed by the at least one execution unit, and wherein the operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and specifies a different second relationship between addresses of sequential accesses within a second address region;
- and
- a programmable address generation accelerator programmed by the operand data structure, wherein the address generation accelerator, responsive to receipt of the initiation signal from the instruction sequencing unit, computes and outputs, to a memory hierarchy including at least one memory external to the processor, first and second effective addresses of operands of an operation in one of the plurality of computation blocks by reference to the first and second relationships specified by the operand data structure.
3 more elements
A method of processing in a processor, comprising:
- with an instruction sequencing unit, sequencing processing of compiled program code by the processor, wherein the compiled program code includes executable instructions, an operand data structure describing a plurality of sequentially processed computation blocks, and block computation commands invoking processing of the computation blocks, wherein the sequencing includes:
- dispatching executable instructions for execution in at least one execution unit of the processor;
- and
- asserting an initiation signal in response to detecting a block computation command in the compiled program code;
- executing the executable instructions in the at least one execution unit;
- buffering operands for access by the at least one execution unit in at least one register file coupled to the at least one execution unit;
- buffering, in data storage of the processor, the operand data structure of the compiled program code, wherein the operand data structure describes the plurality of sequentially processed computation blocks of the compiled program code not executed by the at least one execution unit, and wherein the operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and specifies a different second relationship between addresses of sequential accesses within a second address region;
- and
- in response to the initiation signal of the instruction sequencing unit, a programmable address generation accelerator in the processor computing and outputting, to a memory hierarchy including at least one memory external to the processor, a first effective address and a second effective address of operands of an operation in one of the plurality of computation blocks by reference to the first and second relationships specified by the operand data structure.
6 more elements
Dependencies are inferred from the claim text.