Method for managing a memory apparatus, and associated memory apparatus thereof
AssigneeSilicon Motion, Inc.
InventorsTsai-Cheng Lin, Chun-Kun Lee
Life of this patent
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Abstract
A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table.
Claims8
A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, and a processing unit, the method being performed by the processing unit and comprising:
- providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the at least one local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages;
- and
- building a global page address linking table of the memory apparatus according to the at least one local page address linking table;
- wherein the step of providing the block of the memory apparatus with the local page address linking table within the memory apparatus further comprises:
- building a temporary local page address linking table for the local page address linking table during programming/writing operations of the memory apparatus;
- wherein the step of providing the block of the memory apparatus with the local page address linking table within the memory apparatus further comprises:
- temporarily storing the temporary local page address linking table in a volatile memory of the memory apparatus, and further updating the temporary local page address linking table when any linking relationship between a physical page address and a logical page address of a page in the block is changed.
A memory apparatus, comprising:
- at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks;
- and
- a processing unit arranged to manage the memory apparatus according to a program code embedded in the processing unit or received from outside the processing unit, wherein the processing unit is arranged to provide at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, and the at least one local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages, wherein the processing unit is arranged to build a global page address linking table of the memory apparatus according to the at least one local page address linking table;
- wherein the processing unit builds a temporary local page address linking table for the local page address linking table during programming/writing operations of the memory apparatus;
- and
- wherein before the data pages in the block are fully programmed, the processing unit temporarily stores the temporary local page address linking table in a volatile memory of the memory apparatus, and further updates the temporary local page address linking table when any linking relationship between a physical page address and a logical page address of a page in the block is changed.
Dependencies are inferred from the claim text.