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US 8,285,968 B2Granted
Performing memory accesses while omitting unnecessary address translations
AssigneeInternational Business Machines Corporation
InventorsViktor S. Gyuris, Ali Sheikh, Kirk A. Stewart
Life of this patent
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Abstract
In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.
Claims21
A computer program product for facilitating memory accesses in a computing environment, the computer program product comprising:
- a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- obtaining, by a processor, a first address that indicates an instruction to be executed, the first address being indirectly usable to access memory;
- obtaining, by the processor, the instruction to be executed from a memory location using a second address, the second address provided from a translation of the first address and being directly usable to access memory;
- determining whether the instruction is to access memory;
- based on determining that the instruction is to access memory, determining whether the instruction includes an indicator signifying that the instruction is likely to access operands that are in the same unit of memory as the instruction;
- and
- based on determining that the instruction is to access memory and based on determining that the instruction includes the indicator, checking whether an operand to be accessed by the instruction is in a same unit of memory as the instruction, the checking comprising:
- comparing at least a portion of the first address of the instruction with at least a portion of an operand address of the operand, wherein based on the at least a portion of the first address of the instruction being equal to the at least a portion of the operand address, the instruction and operand are in the same unit of memory;
- and
- based on the checking indicating the operand is in the same unit of memory as the instruction, generating another operand address for the operand, the generating using the second address of the instruction to generate the another operand address for the operand.
7 more elements
A computer system for facilitating memory accesses in a computing environment, the computer system comprising:
- a memory;
- and
- a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
- obtaining a first address that indicates an instruction to be executed, the first address being indirectly usable to access memory;
- obtaining the instruction to be executed from a memory location using a second address, the second address provided from a translation of the first address and being directly usable to access memory;
- determining whether the instruction is to access memory;
- based on determining that the instruction is to access memory, determining whether the instruction includes an indicator signifying that the instruction is likely to access operands that are in the same unit of memory as the instruction;
- and
- based on determining that the instruction is to access memory and based on determining that the instruction includes the indicator, checking whether an operand to be accessed by the instruction is in a same unit of memory as the instruction, the checking comprising:
- comparing at least a portion of the first address of the instruction with at least a portion of an operand address of the operand, wherein based on the at least a portion of the first address of the instruction being equal to the at least a portion of the operand address, the instruction and operand are in the same unit of memory;
- and
- based on the checking indicating the operand is in the same unit of memory as the instruction, generating another operand address for the operand, the generating using the second address of the instruction to generate the another operand address for the operand.
9 more elements
A method of facilitating memory accesses in a computing environment, said method comprising:
- obtaining, by a processor of the computing environment, a first address that indicates an instruction to be executed, the first address being indirectly usable to access memory;
- obtaining, by the processor of the computing environment, the instruction to be executed from a memory location using a second address, the second address provided from a translation of the first address and being directly usable to access memory;
- determining whether the instruction is to access memory;
- based on determining that the instruction is to access memory, determining whether the instruction includes an indicator signifying that the instruction is likely to access operands that are in the same unit of memory as the instruction;
- and
- based on determining that the instruction is to access memory and based on determining that the instruction includes the indicator, checking whether an operand to be accessed by the instruction is in a same unit of memory as the instruction, the checking comprising:
- comparing at least a portion of the first address of the instruction with at least a portion of an operand address of the operand, wherein based on the at least a portion of the first address of the instruction being equal to the at least a portion of the operand address, the instruction and operand are in the same unit of memory;
- and
- based on the checking indicating the operand is in the same unit of memory as the instruction, generating another operand address for the operand, the generating using the second address of the instruction to generate the another operand address for the operand.
6 more elements
Dependencies are inferred from the claim text.