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US 8,285,944 B1Granted
Read-write control of a FIFO memory with packet discard
AssigneeXilinx, Inc.
InventorRoscoe Conkling Nelson, IV
Life of this patent
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Abstract
A write controller controls writing of packet data to a memory, and a read controller controls reading of packet data from the memory. The write controller signals the read controller if a packet is to be discarded. In response to a discard signal from the write controller, the read controller checks whether it is in the midst of processing the packet to be discarded. If the read controller has yet to process the packet to be discarded, then no corrective action is required. However, if the read controller is in the midst of processing the packet to be discarded, then the read controller adjusts its memory read pointer to point to the position in the memory at which it began reading the packet to be discarded.
Claims20
A circuit arrangement for communicating packets of data, comprising:
- a memory;
- a write controller coupled to the memory, wherein the write controller is configured to write words of data packets to the memory addressed by a write pointer from a write pointer register, maintain in a write start address register as each data packet is written to the memory a first address that is an address at which a first word of each data packet is stored in the memory, and generate a first signal in response to a first discard signal;
- wherein for data packets having one word and for data packets having more than one word, the first address of each packet is maintained in the write start address register while writing words of the packet in the memory and updating the write pointer in the write pointer register;
- a read controller coupled to the write controller and to the memory, wherein the read controller is configured to read words of the data packets from the memory addressed by a read pointer from a read pointer register and temporarily maintain in a read start address register as each data packet is read from the memory a second address that is an address from which the first word of each data packet is read from the memory;
- wherein for data packets having one word and for data packets having more than one word, the second address of each packet is maintained in the read start address register while reading words of the packet from the memory and updating the read pointer in the read pointer register;
- wherein the read controller is further configured to compare, in response to the first signal, the first address to the second address, reset the read pointer to the second address in response to the first address being equal to the second address, and not reset the read pointer to the second address in response to the first address being not equal to the second address, and generate a second signal after reset of the read pointer;
- and
- wherein the write controller is further configured to reset the write pointer to the first address in response to the second signal from the read controller.
5 more elements
A method for communicating packets of data, comprising:
- writing words of data packets to a memory addressed by a write pointer from a write point register;
- temporarily storing in a write start address register as each data packet is written to the memory, a first address that is an address at which a first word of each data packet is stored in the memory;
- wherein for data packets having one word and for data packets having more than one word, the first address of each packet is maintained in the write start address register while writing words of the packet in the memory and updating the write pointer in the write pointer register;
- generating a first signal in response to a discard signal;
- reading words of the data packets from the memory addressed by a read pointer from a read pointer register;
- temporarily maintaining in a read start address register as each data packet is read from the memory, a second address that is an address from which the first word of each data packet is read from the memory;
- wherein for data packets having one word and for data packets having more than one word, the second address of each packet is maintained in the read address while reading words of the packet from the memory and updating the read pointer in the read pointer register;
- in response to the first signal from the write controller,
- comparing the first address to the second address,
- resetting the read pointer to the second address in response to the first address being equal to the second address, and
- not resetting the read pointer to the second address in response to the first address being not equal to the second address;
- generating a second signal after resetting the read pointer;
- and
- resetting the write pointer to the first address in response to the second signal.
11 more elements
An apparatus for communicating packets of data, comprising:
- means for writing words of data packets to a memory addressed by a write pointer from a write pointer register;
- means for temporarily storing in a write start address register as each data packet is written to the memory, a first address that is an address at which a first word of each data packet is stored in the memory;
- wherein for data packets having one word and for data packets having more than one word, the first address of each packet is maintained in the write start address register while writing words of the packet in the memory and updating the write pointer in the write pointer register;
- means for generating a first signal in response to a discard signal;
- means for reading words of the data packets from the memory addressed by a read pointer from a read pointer register;
- means for temporarily maintaining in a read start address register as each data packet is read from the memory, a second address that is an address from which the first word of each data packet is read from the memory;
- wherein for data packets having one word and for data packets having more than one word, the second address of each packet is maintained in the read start address register while reading words of the packet from the memory and updating the read pointer in the read pointer register;
- means, responsive to the first signal,
- for comparing the first address to the second address,
- for resetting the read pointer to the second address in response to the first address being equal to the second address, and
- for not resetting the read pointer to the second address in response to the first address being not equal to the second address;
- means for generating a second signal after resetting the read pointer;
- and
- means for resetting the write pointer to the first address in response to the second signal.
11 more elements
Dependencies are inferred from the claim text.