Region coherence array having hint bits for a clustered shared-memory multiprocessor system

A region coherence protocol control system, comprising:

• a system memory;
• a multi-level clustered shared-memory multiprocessor system having multiple levels of interconnect within a hierarchy;
• a region coherence array associated each processor in the clustered shared-memory multiprocessor system to provide a region protocol state of a region of the system memory a logic executing on the multi-level clustered shared-memory multiprocessor system that:
• generates a request for a line of data storable in a system memory;
• in response to a determination that a region protocol state of an entry within a region coherence array of the system indicates that the requested line of data may be cached by processors at multiple levels of interconnect within an interconnect hierarchy of the multi-level clustered shared-memory multiprocessor system, determines whether one or more region hint bits within the region protocol state of an entry in the region coherence array associated with the requesting processor provide an indication that the requested line of data is cached by at least one level of interconnect within interconnect within the multiple levels of interconnect within the interconnect hierarchy of the system, wherein the region hint bits uniquely identify each level of interconnect within the interconnect hierarchy where cached copies of the requested line of data may be stored;
• in response to determining the one or more region hint bits provide an indication that the requested line of data is cached at a specific level of interconnect within the interconnect hierarchy, sends the request to the at least one level of interconnect within the interconnect hierarchy indicated by the region hint bits;
• wherein a level of interconnect is one of a chip level interconnect, a same processor node interconnect or another processor node interconnect;
• wherein the region coherence array is a meta-data array located in a cache hierarchy;
• determines whether the request for the line of data was satisfied by the specific level interconnect indicated by the region hint bits;
• in response to determining the request for the line of data was not satisfied by the specific level of interconnect indicated by the region hint bits, updates, utilizing a most current combined snoop response, the region hint bits to indicate a level of interconnect within the interconnect hierarchy at which the request for the line of data was actually satisfied;
• and
• sends the updated region hint bits to one or more levels of interconnect within the interconnect hierarchy indicated by the region hint bits that do not satisfy the request for the line of data.

A computer program product, comprising:

• a computer readable recording medium;
• and
• program code embodied in said computer readable recording medium that when executed by a computer provides a functionality, including:
• generating a request by a processor for a line of data storable in a system memory;
• in response to a determination that a region protocol state of an entry within a region coherence array of the system indicates that the requested line of data may be cached by processors at multiple levels of interconnect within an interconnect hierarchy of the multi-level system, determining whether one or more region hint bits within the region protocol state of an entry in the region coherence array associated with the requesting processor provide an indication that the requested line of data is cached by at least one of the multiple levels of interconnect within the interconnect hierarchy of the system, wherein the region hint bits uniquely identify each level of interconnect within the interconnect hierarchy where cached copies of the requested line of data may be stored;
• in response to determining the one or more region hint bits provide an indication that the requested line of data is cached at a specific level of interconnect within the interconnect hierarchy, sending the request to the at least one level of interconnect within the interconnect hierarchy indicated by the region hint bits;
• wherein a level of interconnect is one of a chip level interconnect, a same processor node interconnect or another processor node interconnect;
• wherein the region coherence array is a meta-data array located in a cache hierarchy;
• determining whether the request for the line of data was satisfied by the specific level of interconnect indicated by the region hint bits;
• in response to determining the request for the line of data was not satisfied by the specific level of interconnect indicated by the region hint bits, updating, utilizing a most current combined snoop response, the region hint bits to indicate a level of interconnect within the interconnect hierarchy at which the request for the line of data was actually satisfied;
• and
• sending the updated region hint bits to the one or more levels of interconnect within the interconnect hierarchy indicated by the region hint bits that do not satisfy the request for the line of data.