Cache memory with power saving state

A data processing apparatus comprising:

• data processing means for processing data;
• memory means for storing data for use by said data processing means;
• cache memory means for storing cached data from said memory means, said cache memory means comprising a plurality of cache segment means;
• power supply means for selectively supplying each of said cache segment means with power;
• eviction selection means for selecting evictable cached data for eviction from said cache memory means;
• cache compacting means configured to perform cache compaction by evicting said evictable cached data from said cache memory means and storing non-evictable cached data in fewer cache segment means than were used to store said cached data prior to eviction of said evictable cached data;
• and
• power control means configured, to control said power supply means to place in a power saving state at least one of said cache segment means that, following eviction of said evictable cached data by said cache compacting means, are not required to store cached data.

A method for a data processing apparatus comprising data processing circuitry for processing data, a memory for storing data for use by said data processing circuitry, and a cache memory comprising a plurality of cache segments and configured to store cached data from said memory;

• said method comprising the steps of:
• selecting evictable cached data for eviction from said cache memory;
• performing cache compaction by evicting said evictable cached data from said cache memory and storing non-evictable cached data in fewer cache segments than were used to store said cached data prior to eviction of said evictable cached data;
• and
• placing in a power saving state at least one of said cache segments that, following eviction of said evictable cached data, are not required to store cached data.