Methods for adapting performance sensitive operations to various levels of machine loads
AssigneeRed Hat, Inc.
InventorDouglas Ledford
Life of this patent
Estimating the term…
Abstract
For each of a plurality of memory access routines having different access timing characteristic, a redundant array of independent disk (RAID) stack executes the memory access routine to load predetermined data from a main memory to a register of a processor of a data processing system. The RAID stack determines an amount of cache misses for the execution of the memory access routine. The RAID stack selects one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.
Claims21
A computer-implemented method, comprising:
- for each of a plurality of memory access routines having different access timing characteristic, executing, by a redundant array of independent disk (RAID) stack, the memory access routine to load predetermined data from a main memory to a register of a processor of a data processing system;
- determining, by the RAID stack, an amount of cache misses for the execution of the memory access routine;
- and
- selecting, by the RAID stack, one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.
A non-transitory computer readable storage medium including instructions that, when executed by a processing system, cause the processing system to perform a method for parity calculations, the method comprising:
- for each of a plurality of memory access routines having different access timing characteristic, executing, by a redundant array of independent disk (RAID) stack, the memory access routine to load predetermined data from a main memory to a register of a processor of a data processing system;
- determining, by the RAID stack, an amount of cache misses for the execution of the memory access routine;
- and
- selecting, by the RAID stack, one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.
A system, comprising:
- a processor;
- a main memory coupled to the processor;
- and
- a redundant array of independent disk (RAID) stack executed from the main memory to cause the processor to
- for each of a plurality of memory access routines having different access timing characteristic, execute the memory access routine to load predetermined data from the main memory to a register of the processor,
- determine an amount of cache misses for the execution of the memory access routine, and
- select one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.
Dependencies are inferred from the claim text.