Cache access filtering for processors without secondary miss detection

An L2 cache that filters duplicate requests from one or more L1 caches for a cache line, comprising:

• a fill buffer;
• and
• a pending-access status-holding register;
• wherein the pending-access status-holding register is configured to:
• receive a first request and a second request one or more L1 caches;
• and
• store identifying information for the requests;
• and
• wherein the L2 cache is configured to:
• load the cache line into the fill buffer while creating a first load fill packet for the first request;
• preserve the cache line in the fill buffer after sending the first load fill packet to at least one of the one or more L1 caches;
• and
• after sending the first load fill packet, use the loaded fill buffer and the stored information in the pending-access status-holding register to send a subsequent load fill packet for the second request from the L2 cache to at least one of the one or more L1 caches.

A computer system that facilitates cache access filtering, comprising:

• a processor;
• one or more L1 caches that do not support secondary miss detection;
• and
• an L2 cache that includes a fill buffer and a pending-access status-holding register;
• wherein the pending-access status-holding register is configured to:
• receive a first request and a second request from one or more L1 caches;
• and
• store identifying information for the requests;
• and
• wherein the L2 cache is configured to:
• load the cache line into the fill buffer while creating a first load fill packet for the first request;
• preserve the cache line in the fill buffer after sending the first load fill packet to at least one of the one or more L1 caches;
• and
• after sending the first load fill packet, use the loaded fill buffer and the stored information in the pending-access status-holding register to send a subsequent load fill packet for the second request from the L2 cache to at least one of the one or more L1 caches.