Apparatus for enhancing flash memory access
AssigneeScaleo Chip
InventorsPascal Jullien, Cedric Chillie
Life of this patent
Estimating the term…
Abstract
An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.
Claims16
A method for interleaved read access to a plurality of Flash memory units by a controller comprising:
- anticipating, responsive of at least current and past accesses to the plurality of Flash memory units, at least a successive read access request sequential to a current read access request by a processing unit from the plurality of Flash memory units;
- mapping the read access requests to the plurality of Flash memory units to enable the interleaved read access;
- scheduling the interleaved read access requests to the plurality of Flash memory units;
- requesting the interleaved read access from each of the plurality of Flash memory units according to said mapping and said scheduling.
An apparatus for interfacing a Central Processing Unit (CPU) to a plurality of interleaved Flash memory units comprising:
- a bus interface to the CPU for address, memory and control signals;
- an interface to the system clock generator;
- an interface for address, data and control signals for each of the plurality of interleaved Flash memory units;
- an address generation unit enabled to anticipate, responsive of at least current and past accesses to the plurality of Flash memory units, sequential access to the plurality of interleaved Flash memory units and enable to generate interleaved read access requests to the plurality of interleaved Flash memory units.
Dependencies are inferred from the claim text.