Banked memory arbiter for control memory

A data processing device, comprising:

• a memory that includes a plurality of banks;
• a plurality of requestors that generate requests for accessing the memory;
• and
• a control block to:
• receive the requests from the requestors, where the requests are stored in a common memory pool,
• determine, using a result vector:
• the banks to which the requests are intended, and
• one or more of the banks that are available,
• store information in the common memory pool,
• generate a bank vector for each of the banks in the memory, where each of the bank vectors identifies one or more of the requestors generating requests for accessing the memory,
• generate a combined bank vector by concatenating the bank vectors for each of the banks in the memory,
• generate a bank availability vector that identifies which of the banks are available,
• generate a replicated bank availability vector that includes each bit of the bank availability vector,
• generate the result vector based on a combination of the combined bank vector and the replicated bank availability vector, where the result vector indicates that one or more of the banks are available and have a request to be serviced,
• select one or more of the requests to send to the memory based on the result vector, and
• send the selected one or more requests stored in the common memory pool to the memory based on the information stored in the common memory pool.

A device, comprising:

• a memory that includes a plurality of memory parts, each of the memory parts including a plurality of banks;
• a plurality of requestors to issue requests for accessing the memory;
• and
• a control block connected to the plurality of memory parts via a corresponding plurality of buses, the control block to:
• receive the requests, where the requests are stored in a common memory pool,
• determine, using a result vector, the banks:
• to which the requests are intended, and
• that are available for each of the plurality of memory parts;
• generate a bank vector for each of the banks in the memory, where each of the bank vectors identifies one or more of the requestors issuing requests for accessing the memory;
• generate a combined bank vector by concatenating the bank vectors for each of the banks in the memory;
• generate a bank availability vector that identifies which of the banks are available;
• generate a replicated bank availability vector that includes each bit of the bank availability vector;
• generate the result vector based on a combination of the combined bank vector and the replicated bank availability vector, where the result vector indicates that one or more of the banks are available and have a request to be serviced;
• select one or more of the requests to transmit to the memory based on the result vector;
• and
• transmit the selected one or more requests stored in the common memory pool via one or more of the buses based on the information stored in the common memory pool.

A method performed by a device that includes a memory and a plurality of requestors, the memory including a plurality of memory parts, each of the memory parts including a plurality of banks, the requestors issuing requests for accessing the memory, the method comprising:

• receiving the requests from the requestors, where the requests are stored in a common memory pool;
• determining, using a result vector, the banks:
• to which the requests are intended, and
• that are available for each of the plurality of memory parts;
• generating a bank vector for each of the banks in the memory, where each of the bank vectors identifies one or more of the requestors issuing requests for accessing the memory;
• generating a combined bank vector by concatenating the bank vectors for each of the banks in the memory;
• generating a bank availability vector that identifies which of the banks are available;
• generating a replicated bank availability vector that includes each bit of the bank availability vector;
• generating the result vector based on a combination of the combined bank vector and the replicated bank availability vector, where the result vector indicates that one or more of the banks are available and have a request to be serviced;
• selecting one or more of the requests to transmit to the memory based on the result vector;
• and
• transmitting the selected one or more requests stored in the common memory pool to the memory based on the information stored in the common memory pool.

A method performed by a device that includes a memory and a plurality of requestors, the memory including a plurality of memory parts, each of the memory parts including a plurality of banks, the requestors issuing requests for accessing the memory, the method comprising:

• receiving the requests from the requestors, where the requests are stored in a common memory pool;
• determining, using a result vector, the banks:
• to which the requests are intended, and
• that are available for each of the plurality of memory parts;
• generating a bank vector for each of the banks in the memory, where each of the bank vectors identifies one or more of the requestors issuing requests for accessing the memory;
• generating a combined bank vector by concatenating the bank vectors for each of the banks in the memory;
• generating a bank availability vector that identifies which of the banks are available;
• generating a replicated bank availability vector that includes each bit of the bank availability vector;
• generating the result vector based on a combination of the combined bank vector and the replicated bank availability vector, where the result vector indicates that one or more of the banks are available and have a request to be serviced;
• selecting, based on the result vector, a plurality of the requests to transmit to the memory so that multiple ones of the memory parts are serviced in a given clock cycle;
• and
• transmitting the selected requests stored in the common memory pool to the memory in the given clock cycle.