Packet processing in switched fabric networks

A method comprising:

• at a first device operable as a virtual Peripheral Component Interconnect-Express (PCIe) to Advanced Switching (AS) Bridge having an upstream port and N downstream ports,
• processing a PCIe transaction layer packet (TLP) received over a PCIe fabric for transmission over an Advanced Switching Interconnect (ASI) fabric, the processing of the PCIe TLP comprising:
• receiving the PCIe TLP from the PCIe fabric;
• encapsulating the received PCIe TLP by associating one of N downstream ports with an AS path routing header of the PCIe TLP assembled, at least in part, using information in Advanced Switching Configuration Space, and
• transmitting the encapsulated PCIe TLP from the PCIe fabric to the AS fabric;
• and
• processing an ASI packet received over an ASI fabric for transmission over a PCIe fabric, the processing of the ASI packet comprising:
• receiving the ASI packet from the AS fabric;
• associating an AS path routing information in a header of the ASI packet with one of N downstream ports assembled, at least in part, using information in the Advanced Switching Configuration Space, and
• transmitting the processed ASI packet from the AS fabric to the PCIe fabric.

A system comprising:

• a PCIe fabric;
• a first device operative as a virtual Peripheral Component Interconnect-Express (PCIe) to Advanced Switching (AS) Bridge having an upstream port and N downstream ports, the first device including:
• a first interface operatively coupled to the PCIe fabric to pass communication between the PCIe fabric and the first device;
• a second interface operatively coupled to an Advanced Switching Interconnect (ASI) fabric to pass communication between the first device and the ASI fabric;
• and
• a volatile memory operative to store machine-executable instructions to cause a downstream tunneling processor to:
• receive a first packet from the PCIe fabric through the first interface;
• encapsulate the received packet by associating one of N downstream ports with an AS path routing header of the received packet assembled, at least in part, using information in the ASCP, and
• transmit the encapsulated first packet from the PCIe fabric to the AS fabric through the second interface,
• wherein the machine-executable instructions stored in the volatile memory are operative to cause an upstream tunneling processor to:
• receive a second packet from the AS fabric through the second interface,
• associate an AS path routing information in a header of the received second packet with one of N downstream ports assembled, at least in part, using information in the ASCP, and
• transmit the processed second packet from the AS fabric to the PCIe fabric through the first interface.