Requests and data handling in a bus architecture

A bus architecture comprising:

• a bus for connecting at least one master device with at least two slave devices;
• and
• an optimiser for each slave device, each optimiser for buffering incoming requests for the respective slave device;
• wherein the bus is arranged to receive read requests from the master device for the slave devices;
• wherein the architecture is arranged to generate a priority indicator associated with each read request and to generate a current-state indicator associated with each read request;
• and
• wherein each optimiser is arranged to process a read request when the current value of the current-state indicator equals the value of the priority indicator and to defer processing of the read request until a later time when the current value of the current-state indicator does not equal the value of the priority indicator.

A method for processing requests in a bus architecture comprising at least two master devices connected to at least one slave device via a bus, the architecture comprising an optimiser for the or each slave device, each optimiser for buffering incoming requests for the respective slave device, the method comprising the steps of:

• a) a first of the at least two master devices sending a write request for a slave device to the bus;
• b) generating a fence indicator associated with the write request, the fence indicator indicating that the write request to the slave device should be completed before subsequently issued requests from at least the first of the master devices to any slave device are commenced;
• c) sending the fence indicator to the or each optimiser;
• d) each optimiser processing all its requests issued before the write request with which the fence indicator is associated, and the optimiser of the slave device to which the write request was directed further processing the write request itself, and each optimiser deferring the processing of any requests from at least the first master device issued after the write request with which the fence indicator is associated;
• e) each optimiser outputting, once all its requests issued before the write request with which the fence indicator is associated have been processed, and if the optimiser is the optimiser of the slave device to which the write request was directed, once all its requests issued before the write request with which the fence indicator is associated, and the write request itself, have been processed, a completion indicator.

A bus architecture comprising:

• a bus for connecting at least two master devices with at least one slave device;
• and
• an optimiser for the or each slave device, each optimiser for buffering incoming requests for the respective slave device;
• wherein the bus is arranged to receive write requests from the master devices for the slave devices;
• wherein the architecture is arranged to generate a fence indicator associated with at least some write requests, the fence indicator indicating that the write request to the slave device should be completed before subsequently issued requests from at least the first of the master devices are commenced;
• wherein each optimiser is arranged, on receipt of a fence indicator, to process all its requests issued before the write request with which the fence indicator is associated and to defer the processing of any requests from at least the first master device issued after the write request with which the fence indicator is associated, and, once all its requests issued before the write request with which the fence indicator is associated have been processed, to output a completion indicator;
• wherein the optimiser of the slave device to which the write request was directed is further arranged, on receipt of a fence indicator, to process the write request itself and once all its requests issued before the write request with which the fence indicator is associated, and the write request itself, have been processed, to output a completion indicator.

A method for sending data in a bus architecture from at least one slave device to a plurality of master pathways via a bus, the architecture comprising a buffer for buffering data from the at least one slave device, wherein a clock rate of the bus is higher than a clock rate of each master pathway, the method comprising the steps of:

• a) maintaining, in the buffer, a data queue for each master pathway for data received from the slave device;
• b) selecting the data packet at the front of each master pathway queue in the buffer in a round robin manner;
• and
• c) sending, via the bus, the selected data packet to the master pathway to which it is directed.

A bus architecture comprising:

• a bus for connecting a plurality of master pathways with at least one slave device, a clock rate of the bus being higher than a clock rate at each master pathway;
• and
• a buffer for buffering data from the at least one slave device;
• wherein the bus is arranged to maintain, in the buffer, a data queue for each master pathway for data received from the slave device;
• to select the data packet at the front of each master pathway queue in the buffer in a round robin manner;
• and to send the selected data packet to the master pathway to which it is directed.