Handshake free sharing in a computer architecture
AssigneeWinbond Electronics Corp.
InventorsMichal Schramm, Nir Tasher
Life of this patent
Estimating the term…
Abstract
A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.
Claims31
A system arrangement, comprising:
- a memory unit having a memory interface in accordance with a handshake-free protocol between the memory unit and an accessing master;
- a bus connected to the memory unit;
- a first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts, which prevent it from accessing the memory unit, following reception of an interrupt request through an interrupt interface, wherein the first master is operative to perform the interrupts which prevent it from performing its normal processing activities and thus prevent it from accessing the memory unit;
- and
- a second master operative to access the memory unit through the bus and the memory interface, wherein the second master is configured to transfer an interrupt request to the first master before accessing the memory unit and to access the memory unit while the first master is prevented from accessing the memory unit due to the interrupt request.
A processor, comprising:
- a memory interface operative to control a memory unit via a handshake-free protocol;
- an interrupt interface for transfer of interrupt requests to processors;
- and
- a processing unit operative to perform processing tasks and to read data from a memory unit or store data to a memory unit through the memory interface, the processing unit being configured to transfer an interrupt request through the interrupt interface and receive an acknowledgement of the interrupt request before accessing a memory unit through the memory interface and to access the memory unit while a first master is prevented from accessing the memory unit due to the interrupt request, wherein the first master is operative to perform interrupts which prevent it from performing its normal processing activities and thus prevent it from accessing the memory unit.
A method of accessing a memory unit, comprising:
- providing one or more first masters connected to a memory unit;
- determining by a second master that an access to the memory unit is required;
- sending an interrupt request, intended to prevent the one or more first masters from accessing the memory unit, from a second master to the one or more first masters, responsive to the determination that access to the memory unit is required;
- receiving an acknowledgement from the one or more first masters responsive to the interrupt request;
- and
- accessing the memory unit while the one or more first masters are handling the interrupt request,
- wherein the one or more first masters are operative to perform interrupts which prevent them from performing their normal processing activities and thus prevent them from accessing the memory unit.
Dependencies are inferred from the claim text.