Quantum burst arbiter and memory controller

An apparatus comprising:

• means for prioritizing a plurality of channel requests using a first sub-arbiter and a second sub-arbiter, wherein (A) said first sub-arbiter determines a first winning channel based on a first criteria, (B) said second sub-arbiter determines a second winning channel received from said plurality of channel requests based on a second criteria, and (C) each of said plurality of channel requests represent a burst of data having a fixed length aligned to an address boundary of a memory;
• means for (i) receiving a signal indicating said second winning channel and (ii) writing data to a memory using a protocol having a granularity equal to said burst of data, wherein said means for receiving limits access to said granularity during each of a plurality of arbitration cycles;
• and
• means for presenting said plurality of channel requests, wherein (A) said second sub-arbiter is configured to further prioritize the order of said first winning channel by overriding said first winning channel when determining said second winning channel if said second criteria creates a more efficient data transfer and (B) said second criteria of said second sub-arbiter is different than said first criteria of said first sub-arbiter to statistically trade off (i) client bandwidth, (ii) client latency, and (iii) memory protocol efficiency.

A method for implementing a quantum burst arbiter and memory controller, comprising the steps of:

• (A) prioritizing a plurality of channel requests using a first sub-arbiter and a second sub-arbiter, wherein (A) said first sub-arbiter determines a first winning channel based on a first criteria, (B) said second sub-arbiter determines a second winning channel received from said plurality of channel requests based on a second criteria, and (C) each of said plurality of channel requests represent a burst of data having a fixed length aligned to an address boundary of a memory;
• (B) receiving a signal indicating said second winning channel;
• (C) writing data to a memory using a protocol having a granularity equal to said burst of data, wherein said writing is limited to said granularity during each of a plurality of arbitration cycles;
• and
• (D) presenting said plurality of channel requests, wherein (A) said second sub-arbiter is configured to further prioritize the order of said first winning channel by overriding said first winning channel when determining said second winning channel from said first sub-arbiter if said second criteria creates a more efficient data transfer and (B) said second criteria of said second sub-arbiter is different than said first criteria of said first sub-arbiter to statistically trade off (i) client bandwidth, (ii) client latency, and (iii) memory protocol efficiency.