Flattened butterfly processor interconnect network
AssigneeIntel Corporation
InventorsDennis C. Abts, John Kim, William J. Dally
Life of this patent
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Abstract
A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
Claims18
A multiprocessor computer system, comprising a flattened butterfly processor interconnect network, the flattened butterfly interconnect network comprising a network derived from a traditional butterfly processor interconnect network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
A data communication network, comprising a flattened butterfly processor network topology, the flattened butterfly network topology comprising a network derived from a traditional butterfly topology network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
A method of operating a multiprocessor computer system, comprising communicating data between processing nodes via a flattened butterfly processor interconnect network, the flattened butterfly interconnect network comprising a network derived from a traditional butterfly processor interconnect network by flattening routers in each row into a single router for each row and eliminating channels entirely local to the single row.
A method of operating a communications network comprising communicating data in a flattened butterfly processor network topology, the flattened butterfly network topology comprising a network derived from a traditional butterfly topology network by flattening routers in each row into a single router for each row and eliminating channels entirely local to the single row.
A multiprocessor computer system, comprising:
- a flattened butterfly processor interconnect network.
A method of communicating data between processing nodes in a multiprocessor computer system, comprising routing data between nodes in a flattened butterfly topology.
Dependencies are inferred from the claim text.