Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor
AssigneeThe Trustees of Princeton University
InventorsRuby B. Lee, Yedidya Hilewitz
Life of this patent
Estimating the term…
Abstract
Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations.
Claims53
A shifter circuit for a processor, comprising:
- means for obtaining a word in a processor;
- an inverse butterfly circuit connected to said means for obtaining the word, the inverse butterfly circuit including a plurality of circuit stages, each of the circuit stages including a plurality of multiplexers;
- a control circuit in communication with the inverse butterfly circuit for selectively controlling the plurality of multiplexers of the inverse butterfly circuit to perform a bit manipulation operation on the word so as to produce a processed word, the control circuit configured to cause the plurality of multiplexers of the inverse butterfly circuit to perform a parallel extract operation on bits of the word;
- and
- means for supplying the processed word to the processor.
A shifter circuit for a processor, comprising:
- means for obtaining a word in a processor;
- a butterfly circuit connected to said means for obtaining the word, the butterfly circuit including a plurality of circuit stages, each of the circuit stages including a plurality of multiplexers;
- a control circuit in communication with the butterfly circuit for selectively controlling the plurality of multiplexers of the butterfly circuit to perform a bit manipulation operation on the word so as to produce a processed word, the control circuit configured to cause the plurality of multiplexers of the butterfly circuit to perform a parallel deposit operation on bits of the word;
- and
- means for supplying the processed word to the processor.
A shifter functional unit for a processor, comprising:
- an inverse butterfly circuit in communication with a plurality of registers of the processor, the inverse butterfly circuit receiving at least one word from the plurality of registers;
- and
- a control circuit in communication with the inverse butterfly circuit, the control circuit generating and transmitting control bits to the inverse butterfly circuit causing the inverse butterfly circuit to perform a bit manipulation operation on the at least one word to produce a processed word, the control circuit configured to cause the inverse butterfly circuit to perform at least one of a parallel extract or a parallel deposit operation on bits of the word, wherein the inverse butterfly circuit stores the processed word in a location in the plurality of registers for use by the processor.
A method for performing a bit manipulation operation in a processor, comprising the steps of:
- providing a processor having a shifter circuit with an inverse butterfly circuit;
- receiving a word from at least one of a plurality of registers in the processor using the shifter circuit, the word having a first configuration of bits;
- processing the word using a parallel extract or a parallel deposit operation executed by the inverse butterfly circuit of the shifter circuit to create a processed word having a second configuration of bits different than the first configuration of bits;
- and
- transmitting the processed word to the plurality of registers for storage at a location in the plurality of registers and subsequent use by the processor.
Dependencies are inferred from the claim text.