Method and system for equivalence checking
AssigneeAtrenta, Inc.
InventorsSolaiman Rahim, Pradeep Kumar Nalla
Life of this patent
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Abstract
As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating changes the state function it is necessary to perform a sequential equivalence checking (SEC) verification. Applying a full SEC may be runtime consuming and is not scalable for large designs. Methods to reduce the problem of verifying sequential clock gating by reducing the sequential problem into much smaller problem that can be easily solved is therefore shown.
Claims15
A method for performing circuit equivalence check comprising:
- receiving a design of a circuit;
- identifying flip-flops (FFs) of the design which are candidates FFs for observability don't care (ODC) modeling;
- performing ODC modeling and ODC cuts on the identified FF for ODC modeling;
- identifying FFs of the design which are candidates FFs for stability condition (STC) analysis;
- performing STC analysis and STC cuts on the identified FF for STC analysis;
- performing equivalence checks on at least one of the circuits resulting from the ODC cuts and the circuits resulting from the STC cuts;
- and
- reporting circuit equivalence.
A computer program product embodied on tangible media readable by a computing system and on which a plurality of instructions are embedded, wherein the instructions when executed on the computing system perform circuit equivalence check comprising the steps of:
- receiving a design of a circuit;
- identifying flip-flops (FFs) of the design which are candidates FFs for observability don't care (ODC) modeling;
- performing ODC modeling and ODC cuts on the identified FF for ODC modeling;
- identifying FFs of the design which are candidates FFs for stability condition (STC) analysis;
- performing STC analysis and STC cuts on the identified FF for STC analysis;
- performing equivalence checks on at least one of the circuits resulting from the ODC cuts and the circuits resulting from the STC cuts;
- and
- reporting circuit equivalence.
A design system for performing circuit equivalence check comprising:
- a storage;
- a processing unit coupled to the storage;
- and
- at least one of a display or printing unit coupled to processing unit;
- the storage containing a plurality of instructions that when executed on the processing unit perform the tasks of:
- receiving a design of a circuit;
- identifying flip-flops (FFs) of the design which are candidates FFs for observability don't care (ODC) modeling;
- performing ODC modeling and ODC cuts on the identified FF for ODC modeling;
- identifying FFs of the design which are candidates FFs for stability condition (STC) analysis;
- performing STC analysis and STC cuts on the identified FF for STC analysis;
- performing equivalence checks on at least one of the circuits resulting from the ODC cuts and the circuits resulting from the STC cuts;
- and
- reporting circuit equivalence.
Dependencies are inferred from the claim text.