US 8,285,394 B1Granted

Demultiplexer circuit for neural stimulation

AssigneeSandia Corporation

InventorsKurt O. Wessendorf, Murat Okandan, Sean Pearson

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Abstract

A demultiplexer circuit is disclosed which can be used with a conventional neural stimulator to extend the number of electrodes which can be activated. The demultiplexer circuit, which is formed on a semiconductor substrate containing a power supply that provides all the dc electrical power for operation of the circuit, includes digital latches that receive and store addressing information from the neural stimulator one bit at a time. This addressing information is used to program one or more 1:2N demultiplexers in the demultiplexer circuit which then route neural stimulation signals from the neural stimulator to an electrode array which is connected to the outputs of the 1:2N demultiplexer. The demultiplexer circuit allows the number of individual electrodes in the electrode array to be increased by a factor of 2N with N generally being in a range of 2-4.

Claims21

Dependent claims

A demultiplexer circuit formed on a semiconductor substrate, comprising:

a power supply having an energy storage capacitor and a bridge rectifier both formed on the semiconductor substrate, with the power supply receiving an alternating-current (ac) input voltage to generate therefrom all direct-current (dc) electrical power to operate the demultiplexer circuit;
a plurality of latches formed on the semiconductor substrate, with each latch having an ac-coupled input wherein a digital addressing signal is received one bit at a time, with each bit of the digital addressing signal being stored in that latch and provided to an output thereof until such time as a subsequent bit of the digital addressing signal is received at the ac-coupled input of that latch, the ac-coupled input to each latch:
including a coupling capacitor formed from a plurality of metal layers which are stacked up with a dielectric layer separating each adjacent pair of the metal layers;
and
one of the plurality of metal layers forming a bond pad for the ac-coupled input to that latch;
and
at least one 1:2 N demultiplexer formed on the semiconductor substrate, with each 1:2 N demultiplexer having a neural stimulation signal input and an integer number N of addressing inputs, and with the N addressing inputs being connected to the outputs of a set of N of the plurality of latches to receive N bits of the digital addressing signal stored in the set of N latches to program that 1:2 N demultiplexer and thereby connect the neural stimulation signal input to one of 2N outputs for that 1:2 N demultiplexer.

4 more elements

A demultiplexer circuit formed on a semiconductor substrate, comprising:

a power supply having an energy storage capacitor and a bridge rectifier both formed on the semiconductor substrate, with the power supply receiving an alternating-current (ac) input voltage to generate therefrom all direct-current (dc) electrical power to operate the demultiplexer circuit;
a plurality of latches formed on the semiconductor substrate, with each latch having an ac-coupled input wherein a digital addressing signal is received one bit at a time, with each bit of the digital addressing signal being stored in that latch and provided to an output thereof until such time as a subsequent bit of the digital addressing signal is received at the ac-coupled input of that latch, each latch includes:
a reverse-biased diode connected between the input of the first pair of inverters and each power supply connection to that latch;
and
another reverse-biased diode connected between the output of the first pair of inverters and each power supply connection to that latch;
and
at least one 1:2 N demultiplexer formed on the semiconductor substrate, with each 1:2 N demultiplexer having a neural stimulation signal input and an integer number N of addressing inputs, and with the N addressing inputs being connected to the outputs of a set of N of the plurality of latches to receive N bits of the digital addressing signal stored in the set of N latches to program that 1:2 N demultiplexer and thereby connect the neural stimulation signal input to one of 2N outputs for that 1:2 N demultiplexer.

4 more elements

A demultiplexer circuit formed on a semiconductor substrate, comprising:

a power supply having an energy storage capacitor and a bridge rectifier both formed on the semiconductor substrate, with the power supply receiving an alternating-current (ac) input voltage to generate therefrom all direct-current (dc) electrical power to operate the demultiplexer circuit;
a plurality of latches formed on the semiconductor substrate, with each latch having an ac-coupled input wherein a digital addressing signal is received one bit at a time, with each bit of the digital addressing signal being stored in that latch and provided to an output thereof until such time as a subsequent bit of the digital addressing signal is received at the ac-coupled input of that latch;
and
at least one 1:2 N demultiplexer formed on the semiconductor substrate, with each 1:2 N demultiplexer having a neural stimulation signal input and an integer number N of addressing inputs, and with the N addressing inputs being connected to the outputs of a set of N of the plurality of latches to receive N bits of the digital addressing signal stored in the set of N latches to program that 1:2 N demultiplexer and thereby connect the neural stimulation signal input to one of 2N outputs for that 1:2 N demultiplexer;
wherein the semiconductor substrate includes a silicon-on-insulator (SOI) substrate having a monocrystalline silicon base and a monocrystalline silicon layer with an oxide layer being located between the monocrystalline silicon base and the monocrystalline silicon layer.

2 more elements

Dependencies are inferred from the claim text.