Burst mode receiver

A burst mode receiver comprising:

• a limiter amplifier circuit for amplifying a received signal;
• a signal enable determination circuit for determining from the received signal whether a burst signal is in a signal enable period or a signal disable period;
• a CDR circuit for reproducing clock and data from the received signal;
• a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase;
• a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion;
• and
• a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid,
• wherein the CDR output enable determination circuit performs a CDR output enable determination based on a bit synchronization determination result from the bit synchronization determination circuit, a waveform distortion determination result from the waveform distortion determination circuit, and a signal enable determination result from the signal enable determination circuit.