Synchronization determining circuit, receiver including the synchronization determining circuit, and method of the receiver
AssigneeRealtek Semiconductor Corp.
InventorsTzuo-Bo Lin, Bing-Juo Chuang, Yu-Pin Chou
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Abstract
A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.
Claims20
A receiver comprising:
- a data recovery circuit for receiving an input signal, and generating a data signal and a recovery clock;
- a processing circuit, coupled to said data recovery circuit, for processing the data signal to generate a processed signal;
- and
- a determining circuit for determining a synchronization state of the recovery clock according to the processed signal and at least one reference value;
- wherein the data signal includes a synchronous pattern, and the at least one reference value corresponds to at least a portion of the synchronous pattern;
- wherein the determining circuit includes:
- a comparator for comparing a portion of the processed signal and the at least one reference value;
- a counter for generating a counter value according to the comparison result generated by said comparator;
- and
- a determining module for generating the synchronization state of the recovery clock according to the counter value.
A method for determining a synchronization state of a recovery clock of an input signal, said method comprising:
- receiving the input signal;
- generating a data signal and the recovery clock according to the input signal;
- decoding the data signal to generate a decoded signal;
- and
- determining the synchronization state of the recovery clock according to at least one portion of the decoded signal and at least one reference value;
- wherein the data signal includes a synchronous pattern, and said at least one reference value includes a first reference value which corresponds to at least a portion of a first value in the synchronous pattern generated through decoding;
- wherein said step of determining includes comparing the at least one portion of the decoded signal and the first reference value to generate a first comparison result;
- wherein said step of determining further includes comparing the at least one portion of the decoded signal and a second reference value to generate a second comparison result;
- and
- wherein said at least one reference value further includes the second reference value which corresponds to at least a portion of a second value in the synchronous pattern generated through decoding.
A receiver comprising:
- a data recovery circuit for receiving an input signal, and generating a data signal and a recovery clock;
- a processing circuit, coupled to said data recovery circuit, for processing the data signal to generate a processed signal;
- and
- a determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value;
- wherein the data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of the synchronous pattern;
- wherein the synchronous pattern comprises 10′b 0101010101;
- and
- wherein the first reference value comprises at least one of 8′h 4A and 8′h B5.
Dependencies are inferred from the claim text.