Pulse edge demodulation

A system for demodulating a frame of N+1 pulse edges of a pulse edge modulated (PEM) signal to generate an output comprising N data bits, wherein the frame comprises a frame synchronization edge and N modulated edges, each one of the N modulated edges being modulated with a respective one of the N data bits, each one of the N data bits having a value corresponding either to a first state or to a second state and N is an integer greater than one, the system comprising:

• a signal recovery circuit configured to provide a recovered digital carrier signal from the modulated signal, wherein the recovered carrier comprises a pulse train having at least N+1 pulse edges,
• wherein one edge of the recovered carrier is coincident with the frame synchronization edge, the frame synchronization edge comprises an unmodulated edge of the PEM signal;
• and
• a demodulator configured to demodulate each one of the N modulated edges of the PEM signal and to provide an output corresponding to the state of each one of the respective N data bits,
• wherein demodulating each one of the N modulated edges determines whether a modulated edge has a first position in time or a second position in time relative to the position in time of the modulated edge prior to modulation, and
• wherein the first position in time of the modulated edge corresponds to the first state of a data bit and the second position in time of the modulated edge corresponds to a second state of a data bit.

A demodulator, configured to demodulate a frame of a pulse edge modulated (PEM) signal and generate an output comprising N data bits, the demodulator arranged to receive the frame of the PEM signal, wherein the frame of the PEM signal comprises a frame synchronization edge and N modulated edges, each one of the N modulated edges being modulated with a respective one of the N data bits, wherein each one of the N data bits has a value corresponding either to a first state or to a second state and N is an integer greater than one, the demodulator comprising:

• a phase locked loop configured to generate a clock signal from the received PEM signal;
• means for dividing the clock to generate a first reference signal, wherein the first reference signal comprises a pulse train having at least N+1 edges;
• means for generating a second reference signal delayed by a first amount of time relative to the first reference signal, wherein the second reference signal comprises a recovered clock signal;
• means for generating a third reference signal delayed by a second amount of time relative to the second reference signal;
• and
• an edge discriminator configured to demodulate the N edges of the PEM signal,
• wherein the edge discriminator is configured to:
• a.) receive the PEM signal and at least the first and third reference signals, and
• b.) to generate N digital data bits corresponding to the received respective N modulated edges of the PEM signal.

A process for demodulating a modulated edge of a pulse edge modulated (PEM) signal, wherein the modulated edge has either a first position in time or a second position in time relative to an associated timing reference edge of a recovered digital carrier signal, a value of a data bit being modulated on the modulated edge and the value of the data bit corresponds either to a first state or to a second state, the process comprising:

• generating a recovered digital carrier signal from the modulated PEM signal;
• selecting an edge of the recovered carrier corresponding to the modulated edge as an associated timing reference edge, wherein the associated timing reference edge represents the position in time of the modulated edge prior to modulation;
• and
• demodulating the modulated edge and providing an output corresponding to the state of the data bit,
• wherein demodulating the modulated edge comprises determining the position of the modulated edge relative to the associated timing reference edge, by determining that the modulated edge has either a first position or a second position in time relative to the associated timing reference edge, and
• wherein the first position in time corresponds to a first state of the data bit and the second position in time corresponds to a second state of the data bit.

A process for demodulating a frame of N+1 pulse edges of a pulse edge modulated (PEM) signal to generate an output of N data bits, wherein the frame comprises a frame synchronization edge and N modulated edges, each one of the N modulated edges being modulated with a respective one of the N data bits, each one of the N data bits having a value corresponding either to a first state or to a second state and N is an integer greater than one, the process comprising:

• recovering a digital carrier signal from the PEM signal, wherein the carrier comprises a pulse train having at least N+1 pulse edges;
• wherein each one of N edges of the recovered carrier is associated with a respective edge of the N modulated edges of the PEM signal, and each edge of the recovered carrier associated with a respective modulated edge represents the position in time of the respective modulated edge prior to modulation;
• detecting the frame synchronization edge of the PEM signal, wherein the frame synchronization edge is an unmodulated edge;
• and
• demodulating each one of the N modulated edges of the PEM signal to provide an output corresponding to the state of each one of the respective N data bits,
• wherein demodulating each one of the N modulated edges comprises determining whether the modulated edge has a first position in time or a second position in time relative to its associated respective edge of the recovered carrier, and
• wherein the first position in time corresponds to the first state of a data bit and the second position in time corresponds to the second state of a data bit.