A shared processor architecture in a receiver system, the receiver system configured to have a first functional stage and a second functional stage for processing information carried by signals from a first communication system and a second communication system respectively, the first functional stage and the second functional stage corresponding to an identical signal processing function, the shared processor architecture comprising:
- a first processor, allocated to the first functional stage and the second functional stage, for processing an output generated from the first functional stage or an output from the second functional stage;
- and
- a time base generator, managed by the first processor and allocated to the first functional stage and the second functional stage, for providing a plurality of time bases to the first functional stage and the second functional stage respectively.