Ethernet system and related clock synchronization method

A synchronization method for a master device in an Ethernet system, the synchronization method comprising:

• generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode, the transmission data comprising phase information of a recovery clock of the slave device;
• accumulating the phase adjustment data and outputting a phase adjustment value;
• adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock;
• and
• transmitting initialization data to the slave device, during the switch mode, according to the phase-adjusted output clock.

A master device for an Ethernet system, for synchronizing with a slave device, the master device comprising:

• a receiver for receiving transmission data from a slave device, the transmission data comprising phase information of a recovery clock;
• a transmitter operating according to a first clock;
• a detection unit coupled to the receiver and the transmitter for detecting a phase difference between clocks of the master device and the slave device according to the first clock and the recovery clock;
• and
• a synchronization unit, coupled to the detection unit, for comparing the phase difference with a tolerance value and controlling the master device to wake from a quiet mode and execute a process for synchronization with the slave device when the phase difference exceeds the tolerance value, and allowing the master device to remain in a quiet mode when the phase difference does not exceed the tolerance value.

A method for performing synchronization between a master device and a slave device in an Ethernet system, the method comprising:

• receiving transmission data from the slave device, the transmission data comprising phase information of a recovery clock;
• detecting a phase difference between clocks of the master device and the slave device according to the first clock and the recovery clock;
• and
• comparing the phase difference with a tolerance value, and controlling the master device to wake up from a sleep mode and execute a process for synchronization with the slave device when the phase difference exceeds the tolerance value, and allowing the master device to remain in a quiet mode when the phase difference does not exceed the tolerance value.