Multi-core processor and method of communicating across a die

A die comprising:

• a first core on the die, a second core on the die and a third core on the die;
• a first interconnect between the first core and the second core;
• and
• a second interconnect between the second core and the third core, and the first, second and third cores on the die to communicate across the die using resources of a packet switched network when sending a control portion of a packet across the die, and the first, second and third cores on the die to communicate using resources of a circuit switched network when sending a data portion of the packet across the die.

A method of communicating on a multi-core die, the method comprising:

• sending a control portion of a packet from a first core of the multi-core die, through a second core of the multi-core die to a third core of the multi-core die using resources of a packet switched network and without simultaneously sending a corresponding data portion of the packet;
• sending an acknowledgment from the third core of the multi-core die to the first core of the multi-core die in response to the third core receiving the control portion of the packet;
• and
• sending a data portion of the packet from the first core of the multi-core die through the second core of the multi-core die and to the third core of the multi-core die using resources of a circuit switched network in response to the first core of the multi-core die receiving the acknowledgement.