Estimating data throughput

A device, comprising:

• an output interface;
• and
• logic configured to:
• transmit, via the output interface, a first data burst and a second data burst to a network or circuit under test, the first data burst having a first size and the second data burst have a second size, wherein the first size is less than the second size,
• determine a first latency associated with the first data burst,
• determine a second latency associated with the second data burst,
• generate an estimated latency based on the first and second latencies,
• generate a first value based on the first and second sizes, and
• calculate an estimated throughput of the network or circuit under test based on a difference in the first and second latencies, a difference in the first and second sizes of the first and second data bursts, and a first rate at which the first and second data bursts were transmitted, wherein when calculating an estimated throughput, the logic is configured to:
• divide the first value by the first rate to generate a second value,
• add the estimated latency to the second value to generate a third value,
• divide the second value by the third value to generate a fourth value, and
• multiply the fourth value by the first rate to generate the estimated throughput.

A non-transitory computer-readable medium having stored thereon sequences of instructions which, when executed by at least one processor, cause the at least one processor to:

• signal a data source to transmit a first data burst and a second data burst to a network or circuit under test at a first data rate, the first data burst having a first size and the second data burst have a second size, wherein the first size is less than the second size;
• calculate an estimated latency for the network or circuit under test based on time information associated with the first and second data bursts;
• calculate an estimated incremental burst size based on the first and second sizes of the first and second data bursts, and
• calculate an estimated throughput of the network or circuit under test based on the estimated latency, a difference in the first and second sizes of the first and second data bursts, and the first data rate, wherein when calculating an estimated throughput, the instructions cause the at least one processor to:
• divide the estimated incremental burst size by the first data rate to generate a first value,
• add the estimated latency to the first value to generate a second value,
• divide the first value by the second value to generate a third value, and
• multiply the third value by the first data rate to generate a fourth value, the fourth value representing the estimated throughput.