Voltage regulator for memory

A voltage regulator for memory, comprising:

• a first transistor, having a first end electrically connected to an input node, a second end electrically connected to an output node, and a control end, the input node electrically connected to a voltage source;
• a second transistor, having a first end electrically connected to the input node, a second end electrically connected to the output node, and a control end;
• a digital boosting control circuit, electrically connected to the control end of the second transistor, to control the second transistor according to a first input signal;
• and
• an analog boosting control circuit, electrically connected to the control end and the output node of the first transistor, to control the first transistor according to a second input signal and a voltage of the output node;
• wherein the analog boosting control circuit controls the first transistor according to the second input signal and the voltage of the output node a predetermined time after the digital boosting control circuit turns on the second transistor according to the first input signal and then the digital boosting control circuit turns off the second transistor so that a voltage of the control end of the first transistor inclines to a first voltage level after the second input signal is triggered and to a second voltage level after the second transistor is turned off.