Semiconductor device having memory blocks
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKiyoshi Kato
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Abstract
A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.
Claims30
A semiconductor device comprising:
- a plurality of memory blocks;
- a control circuit;
- and
- a power supply circuit,
- wherein each of the memory blocks comprises:
- a memory cell array including a plurality of memory cells each having a memory element in a region where a bit line and a word line cross each other with an insulator interposed therebetween;
- and
- a row decoder electrically connected to the memory cell array,
- wherein the control circuit is configured to output first control signals and second control signals and to set each of the memory blocks to a normal mode or a standby mode,
- wherein each one of the first control signals controls a first power supply potential supplied to a corresponding one of the memory cell array of the memory blocks, and
- wherein each one of the second control signals controls a second power supply potential supplied to a corresponding one of the row decoder of the memory blocks.
A semiconductor device comprising:
- a plurality of memory blocks;
- a control circuit;
- a power supply circuit;
- and
- a plurality of switches provided between the memory blocks and the power supply circuit, wherein each of the plurality of switches corresponds to one of the plurality of memory blocks,
- wherein each of the memory blocks comprises:
- a memory cell array including a plurality of memory cells each having a memory element in a region where a bit line and a word line cross each other with an insulator interposed therebetween;
- and
- a row decoder electrically connected to the memory cell array,
- wherein the control circuit is configured to output first control signals and second control signals to the plurality of switches, and to set each of the memory blocks to a normal mode or a standby mode,
- wherein each one of the first control signals controls a first power supply potential supplied to a corresponding one of the memory cell array of the memory blocks, and
- wherein each one of the second control signals controls a second power supply potential supplied to a corresponding one of the row decoder of the memory blocks.
A semiconductor device comprising:
- a CPU;
- a control circuit operationally connected to the CPU;
- a first memory block and a second memory block, each comprising a memory cell array and a decoder;
- a first switch configured to selectively supply the first memory block with one of a first potential and a second potential in accordance with a first control signal from the control circuit;
- and
- a second switch configured to selectively supply the second memory block with one of the first potential and the second potential in accordance with a second control signal from the control circuit.
A semiconductor device comprising:
- a CPU;
- a control circuit operationally connected to the CPU;
- a first memory block and a second memory block, each comprising a memory cell array and a decoder;
- a first switch configured to selectively supply the memory cell array of the first memory block with one of a first potential and a second potential in accordance with a first control signal from the control circuit;
- a second switch configured to selectively supply the memory cell array of the second memory block with one of the first potential and the second potential in accordance with a second control signal from the control circuit;
- a third switch configured to selectively supply the decoder of the first memory block with one of a third potential and a fourth potential in accordance with a third control signal from the control circuit;
- and
- a fourth switch configured to selectively supply the decoder of the second memory block with one of the third potential and the fourth potential in accordance with a fourth control signal from the control circuit.
Dependencies are inferred from the claim text.