Level detector, internal voltage generator including level detector, and semiconductor memory device including internal voltage generator
AssigneeSamsung Electronics Co., Ltd.
InventorsKi-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee
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Abstract
A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.
Claims19
A level detector, comprising:
- a differential amplifying unit configured to output a differentially amplified comparative voltage at a second node in response to a voltage at a first node that varies based upon a difference between a reference voltage and a sensed voltage;
- and
- a temperature coefficient adjustment unit configured to control current that flows through the first node in response to a variable voltage having a level that varies with temperature, and to control current that flows through the second node in response to a fixed voltage having a level that does not vary with temperature,
- wherein the differential amplifying unit comprises:
- a reference voltage generator configured to receive an external constant voltage and to output the reference voltage;
- a sensed voltage generator configured to output the sensed voltage in response to an input voltage;
- and
- a differential amplifier that is driven by a first current source and configured to output a voltage at the second node that varies based upon the voltage at the first node, as the differentially amplified comparative voltage,
- wherein the reference voltage and the sensed voltage do not vary with temperature.
An internal voltage generator comprising:
- a level detector configured to compare a reference voltage with a sensed voltage that varies based upon temperature and to output a comparative voltage;
- and
- an internal voltage driver configured to adjust an external supply voltage in response to the comparative voltage and to output the internal voltage,
- wherein the level detector comprises:
- a comparative voltage generator configured to output the comparative voltage in response to a difference between the reference voltage and the sensed voltage;
- and
- a sensed voltage generator comprising a first resistance unit and a second resistance unit connected in series between an output node for the internal voltage and a ground voltage and that outputs the sensed voltage that varies with temperature,
- wherein the second resistance unit has a resistance that varies with temperature.
An internal voltage generator comprising:
- a level detector configured to compare a reference voltage a sensed voltage that varies based upon temperature and to output a comparative voltage;
- and
- an internal voltage driver configured to adjust an external supply voltage in response to the comparative voltage and to output the internal voltage,
- wherein the level detector comprises:
- a differential amplifying unit configured to output a differentially amplified comparative voltage at a second node in response to a voltage at a first node that varies based upon a difference between the reference voltage and the sensed voltage;
- and
- a temperature coefficient adjustment unit configured to control current that flows through the first node in response to a variable voltage having a level that varies with temperature, and to control current that flows through the second node in response to a fixed voltage having a level that does not vary with temperature.
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines;
- a sense amplifier configured to sense and to amplify a signal on a corresponding bit line of the plurality of bit lines in response to a sense enable signal;
- a controller configured to receive an internal voltage, to drive a corresponding word line of the plurality of word lines in response to an external command and to output the sense enable signal;
- and
- an internal voltage generator comprising:
- a level detector configured to compare a threshold voltage that varies with temperature and the internal voltage to output a comparative voltage, and
- an internal voltage driver configured to adjust an external supply voltage in response to the comparative voltage and to output the internal voltage,
- the internal voltage generator is configured to output an internal voltage that is lower at low temperature than the internal voltage at high temperature, and
- the controller is configured to adjust a delay time until the sense enable signal is output after the word line is driven, using the internal voltage.
A semiconductor memory device comprising:
- a memory array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines;
- a sense amplifier configured to sense and to amplify a signal on a corresponding bit line of the plurality of bit lines in response to a sense enable signal;
- a controller configured to receive an internal voltage, to drive a corresponding word line of the plurality of word lines in response to an external command, and to output the sense enable signal;
- and
- an internal voltage generator comprising:
- a level detector configured to compare a threshold voltage that varies with temperature and the internal voltage to output a comparative voltage, and
- an internal voltage driver configured to adjust an external supply voltage in response to the comparative voltage and to output the internal voltage,
- a comparative voltage generator configured to output the comparative voltage in response to a difference between a reference voltage and a sensed voltage;
- and
- a sensed voltage generator comprising a first resistance unit and a second resistance unit connected in series between an output node for the internal voltage and a ground voltage and that outputs the sensed voltage that varies with temperature,
- wherein the second resistance unit has a resistance that varies with temperature.
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines;
- a sense amplifier configured to sense and to amplify a signal on a corresponding bit line of the plurality of bit lines in response to a sense enable signal;
- a controller configured to receive an internal voltage, to drive a corresponding word line of the plurality of word lines in response to an external command, and to output the sense enable signal;
- and
- an internal voltage generator comprising:
- a level detector configured to compare a threshold voltage that varies with temperature and the internal voltage to output a comparative voltage, and
- an internal voltage driver configured to adjust an external supply voltage in response to the comparative voltage and to output the internal voltage,
- wherein the level detector comprises:
- a differential amplifying unit configured to output a differentially amplified comparative voltage to a second node in response to a voltage at a first node that varies with a difference between a reference voltage and a sensed voltage;
- and
- a temperature coefficient adjustment unit configured to control current that flows through the first node in response to a variable voltage having a level that varies with temperature, and to control current that flows through the second node in response to a fixed voltage having a level that does not vary with temperature.
Dependencies are inferred from the claim text.