Memory device with phase distribution circuit for controlling relative durations of precharge and active phases

A phase distribution circuit for controlling durations of precharge and active phases of a memory cycle in a memory device, comprising:

• a first tracking transistor of a first conductivity type for tracking a precharge transistor of the memory device;
• a second tracking transistor of a second conductivity type different than the first conductivity type for tracking a memory cell transistor of the memory device;
• and
• first and second inverters, with an output of the first inverter coupled to an input of the second inverter, and wherein the first and second tracking transistors have their gate terminals coupled to an output of the second inverter and their source or drain terminals coupled to the output of the first inverter, such that the first tracking transistor is operative to oppose a signal transition in a first direction at the output of the first inverter and the second tracking transistor is operative to oppose a signal transition in a second direction at the output of the first inverter;
• wherein the phase distribution circuit is operative to control the durations of the precharge and active phases of the memory cycle based on relative transistor characteristics of the tracked precharge and memory cell transistors.

A method comprising:

• tracking a characteristic of a precharge transistor of a memory device;
• tracking a characteristic of a memory cell transistor of a memory device;
• and
• controlling durations of precharge and active phases of a memory cycle of the memory device based on relative characteristics of the tracked precharge and memory cell transistors.