Strobe offset in bidirectional memory strobe configurations

A method of determining correct timing for data strobe reception, by a host in a memory system, of a normal toggle transmitted by an addressed memory chip, the method comprising:

• establishing an offset on a data strobe;
• assuming, in the host, an initial timing for reception of the normal toggle;
• iterating on the following blocks:
• transmitting a read command to the addressed memory chip, the addressed memory chip responding by transmitting a normal toggle on the data strobe;
• receiving the normal toggle in the host;
• when the normal toggle is correctly received in the host, then storing the timing and ending the iteration;
• and
• when the normal toggle is not correctly received in the host, adjusting the timing.

A method of determining correct timing of a DQS receiver enable in a first semiconductor chip connected to one or more second semiconductor chips using a bidirectional data strobe, the method comprising:

• transmitting a first Mode Register Set (MRS) command to set a DQS drive bit on an addressed second semiconductor chip to an active state on the addressed second semiconductor chip;
• assuming an initial timing for a DQS receiver enable;
• iteratively performing the following blocks:
• issuing a read command to the addressed second semiconductor chip;
• determining if timing of the DQS receiver enable is correct;
• when the timing of the DQS receiver is correct, issuing a second MRS command to set the DQS drive bit to an inactive state on the addressed second semiconductor chip and ending the iteration;
• and
• when the timing of the DQS receiver is not correct, adjusting the timing of the DQS receiver enable and continuing the iteration.