US 8,284,620 B2 · Memory controller-adaptive 1T/2T timing control

Abstract

Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.

Claims20

Dependent claims

An integrated circuit comprising a memory controller interface comprising:

a first plurality of address lines coupled to a first memory circuit;
a first plurality of control lines coupled to the first memory circuit;
a second plurality of address lines coupled to a second memory circuit;
and
a second plurality of control lines coupled to the second memory circuit,
wherein when a first control line in the first plurality of control lines is also coupled to the second memory circuit and the memory controller interface operates at an interface frequency below a first frequency, then the first control line operates at a first rate;
and
wherein when the first control line is not also coupled to the second memory and the interface frequency is below a second frequency, the second frequency higher than the first frequency, then the first control line also operates at the first rate,
otherwise the first control line operates at the second rate, where the first rate is faster than the second rate,
wherein when the first control line is not also coupled to the second memory and the memory controller interface operates at a frequency above the second frequency, then the first control line operates at the second rate.

7 more elements

An integrated circuit comprising a memory controller interface comprising:

a first plurality of address lines coupled to a first memory circuit;
a first plurality of control lines coupled to the first memory circuit;
a second plurality of address lines coupled to a second memory circuit;
and
a second plurality of control lines coupled to the second memory circuit,
wherein when a first control line in the first plurality of control lines is also coupled to the second memory circuit and the memory controller interface operates at an interface frequency below a first frequency, then the first control line operates at a first rate;
and
wherein when the first control line is not also coupled to the second memory and the interface frequency is below a second frequency, the second frequency higher than the first frequency, then the first control line also operates at the first rate,
otherwise the first control line operates at the second rate, where the first rate is faster than the second rate,
wherein a second control line in the first plurality of control lines operates at a different rate than the first control line, and
wherein the first and second control lines respectively carry a signal selected from a group consisting of a row address select signal, a column address select signal, a write enable signal, and a chip enable signal.

8 more elements

An integrated circuit comprising:

a first memory interface comprising a first plurality of address lines and a first plurality of control lines;
a second memory interface comprising a second plurality of address lines and a second plurality of control lines;
and
a control circuitry configured to:
identify a number of memory devices to be driven by each of the first plurality of address lines and each of the first plurality of control lines;
and
individually disable each of the first plurality of address lines and the first plurality of control lines that are not used to drive a memory device,
wherein after an address line or a control line has been disabled, that disabled line is not used by the first memory interface to send a signal to a memory device,
wherein a result of a control line of the first plurality of control lines being disabled is that a corresponding control line of the second plurality of control lines is enabled, and
wherein the control circuitry is further configured to determine whether each of the first plurality of address lines and each of the first plurality of control lines are disabled, operating at 1T timing, or operating at 2T timing, wherein when a line operates at 1T timing it has a rate that is twice the rate as when the line operates at 2T timing.

7 more elements

Dependencies are inferred from the claim text.

Memory controller-adaptive 1T/2T timing control

Life of this patent

Memory controller-adaptive 1T/2T timing control

Life of this patent

Abstract

Claims20