Trench memory structure operation
AssigneeMicron Technology, Inc.
InventorRamin Ghodsi
Life of this patent
Estimating the term…
Abstract
Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls.
Claims20
A method of programming a target memory cell in an array of memory cells, comprising:
- applying a first potential to a first control gate overlying an active area of the target memory cell, wherein the target memory cell comprises a first charge trapping region on a first side of the first control gate, and a second charge trapping region on a second side of the first control gate opposing the first side of the first control gate;
- applying a second potential to a second control gate having a first portion overlying the first control gate and a second portion adjacent to the first control gate;
- and
- injecting charge into at least one charge trapping region of the target memory cell in response, at least in part, to the first potential and the second potential.
A method of programming a target memory cell in an array of memory cells, comprising:
- applying a first potential to a first control gate overlying an active area of the target memory cell;
- applying a second potential to a second control gate having a first portion overlying the first control gate and a second portion adjacent to the first control gate;
- applying a third potential to a particular one of a bit line associated with the target memory cell and a source line associated with the target memory cell;
- allowing the other one of the bit line associated with the target memory cell and the source line associated with the target memory cell to float;
- and
- injecting charge into a charge trapping region of the target memory cell in response, at least in part, to the first potential and the second potential, wherein the charge trapping region of the target memory cell is adjacent the first control gate and nearest the particular one of the bit line associated with the target memory cell and the source line associated with the target memory cell.
A method of programming a target memory cell in an array of memory cells, comprising:
- applying a first potential to a first control gate overlying an active area of the target memory cell sufficient to invert a channel under the first control gate;
- applying a second potential to a second control gate having a first portion overlying the first control gate, a second portion adjacent to a first side of the first control gate and a third portion adjacent to a second side of the first control gate opposing the first side of the first control gate;
- and
- injecting charge into charge trapping regions of the target memory cell in response, at least in part, to the first potential and the second potential;
- wherein the charge trapping regions of the target memory cell are between the second portion of the second control gate and the third portion of the second control gate.
Dependencies are inferred from the claim text.